From 9c11631f94ec9d431a85b67d54c8c720d61f8c90 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Sun, 3 Jul 2022 03:43:50 -0700 Subject: [PATCH] re-reserve bit in setvl -- needed for extending registers: https://bugs.libre-soc.org/show_bug.cgi?id=535 --- openpower/sv/setvl.mdwn | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn index d6cb15dc0..f5e66c42a 100644 --- a/openpower/sv/setvl.mdwn +++ b/openpower/sv/setvl.mdwn @@ -89,7 +89,11 @@ Instruction format: setvl RT,RA,SVi,vf,vs,ms setvl. RT,RA,SVi,vf,vs,ms -Note that the immediate (`SVi`) spans 7 bits (16 to 22) +Note that the immediate (`SVi`) spans 7 bits (16 to 22). + +Instruction encodings where `SVi`'s MSB is set are reserved for future extensions. +Implementations are required to cause an illegal instruction exception when +`SVi`'s MSB is set to allow software emulation of those future extensions. * `ms` - bit 23 - allows for setting of MVL * `vs` - bit 24 - allows for setting of VL -- 2.30.2