From 9c15c7d7da6bcda7c78184b811603bda086a0002 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 16 Sep 2021 11:28:44 +0100 Subject: [PATCH] --- openpower/sv/svp64/appendix.mdwn | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn index a556a8786..7ea6676aa 100644 --- a/openpower/sv/svp64/appendix.mdwn +++ b/openpower/sv/svp64/appendix.mdwn @@ -210,6 +210,20 @@ Scalar reduction is thus categorised by: `setb` or `isel` makes no sense for example because of the mixture between CRs and GPRs. +*Note that issuing instructions in Scalar reduce mode such as `setb` +are neither `UNDEFINED` nor prohibited, despite them not making much +sense at first glance. +Scalar reduce is strictly defined behaviour, and the cost in +hardware terms of prohibition of seemingly non-sensical operations is too great. +Therefore it is permitted and required to be executed successfully. +Implementors **MAY** choose to optimise such instructions in instances +where their use results in "extraneous execution", i.e. where it is clear +that the sequence of operations, comprising multiple overwrites to +a scalar destination **without** cumulative, iterative, or reductive +behaviour, may discard all but the last element operation. Identification +of such is trivial to do for `setb` and `cmp`: the source register type is +a completely different register file from the destination* + Typical applications include simple operations such as `ADD r3, r10.v, r3` where, clearly, r3 is being used to accumulate the addition of all elements is the vector starting at r10. -- 2.30.2