From 9c233cbd457dd262e78d5b9c33b3aa4fb82febb7 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 16 Apr 2021 23:47:15 +0100 Subject: [PATCH] single-cycle mode fix on wb "wen" signal, must hold fully until ACKed --- c4m/nmigen/jtag/tap.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/c4m/nmigen/jtag/tap.py b/c4m/nmigen/jtag/tap.py index 1197e38..1f3d424 100755 --- a/c4m/nmigen/jtag/tap.py +++ b/c4m/nmigen/jtag/tap.py @@ -800,6 +800,7 @@ class TAP(Elaboratable): if hasattr(wb, "stall"): m.d.comb += wb.stb.eq(fsm.ongoing("READ") | fsm.ongoing("WRITEREAD")) + m.d.comb += wb.we.eq(fsm.ongoing("WRITEREAD")) else: # non-stall is single-cycle (litex), must assert stb # until ack is sent @@ -807,7 +808,6 @@ class TAP(Elaboratable): fsm.ongoing("WRITEREAD") | fsm.ongoing("READACK") | fsm.ongoing("WRITEREADACK")) - m.d.comb += [ - wb.cyc.eq(~fsm.ongoing("IDLE")), - wb.we.eq(fsm.ongoing("WRITEREAD")), - ] + m.d.comb += wb.we.eq(fsm.ongoing("WRITEREAD") | + fsm.ongoing("WRITEREADACK")) + m.d.comb += wb.cyc.eq(~fsm.ongoing("IDLE")) -- 2.30.2