From 9c2d308c97bbd31665deaa7c0901b6fad11ada65 Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Fri, 15 Apr 2022 18:03:57 +0200 Subject: [PATCH] add orangecrab to list of supported boards --- src/ls2.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ls2.py b/src/ls2.py index 50d69e1..d953350 100644 --- a/src/ls2.py +++ b/src/ls2.py @@ -283,7 +283,7 @@ class DDR3SoC(SoC, Elaboratable): # set up clock request generator pod_bits = 25 - if fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim', 'ulx3s']: + if fpga in ['versa_ecp5', 'versa_ecp5_85', 'isim', 'ulx3s', 'orangecrab']: if fpga in ['isim']: pod_bits = 6 self.crg = ECP5CRG(clk_freq, dram_clk_freq=None, pod_bits=pod_bits) -- 2.30.2