From 9c4dcbe4e4dc3a266c4d443e0eb2e63a8219b7d5 Mon Sep 17 00:00:00 2001 From: Dmitry Selyutin Date: Mon, 29 May 2023 01:04:57 +0300 Subject: [PATCH] ppc: support ffmsubs instruction --- gas/testsuite/gas/ppc/ffmsubs.d | 14 ++++++++++++++ gas/testsuite/gas/ppc/ffmsubs.s | 6 ++++++ gas/testsuite/gas/ppc/ppc.exp | 1 + opcodes/ppc-opc.c | 3 +++ 4 files changed, 24 insertions(+) create mode 100644 gas/testsuite/gas/ppc/ffmsubs.d create mode 100644 gas/testsuite/gas/ppc/ffmsubs.s diff --git a/gas/testsuite/gas/ppc/ffmsubs.d b/gas/testsuite/gas/ppc/ffmsubs.d new file mode 100644 index 00000000000..d35916083c3 --- /dev/null +++ b/gas/testsuite/gas/ppc/ffmsubs.d @@ -0,0 +1,14 @@ +#as: -mlibresoc +#objdump: -dr -Mlibresoc + +.*: file format .* + + +Disassembly of section \.text: +0+ <\.text>: +.*:\s+(ef e0 00 08|08 00 e0 ef)\s+ffmsubs\s+f31,f0,f0 +.*:\s+(ec 1f 00 08|08 00 1f ec)\s+ffmsubs\s+f0,f31,f0 +.*:\s+(ec 00 f8 08|08 f8 00 ec)\s+ffmsubs\s+f0,f0,f31 +.*:\s+(ef e0 00 09|09 00 e0 ef)\s+ffmsubs.\s+f31,f0,f0 +.*:\s+(ec 1f 00 09|09 00 1f ec)\s+ffmsubs.\s+f0,f31,f0 +.*:\s+(ec 00 f8 09|09 f8 00 ec)\s+ffmsubs.\s+f0,f0,f31 diff --git a/gas/testsuite/gas/ppc/ffmsubs.s b/gas/testsuite/gas/ppc/ffmsubs.s new file mode 100644 index 00000000000..e1d97b62674 --- /dev/null +++ b/gas/testsuite/gas/ppc/ffmsubs.s @@ -0,0 +1,6 @@ +ffmsubs 31,0,0 +ffmsubs 0,31,0 +ffmsubs 0,0,31 +ffmsubs. 31,0,0 +ffmsubs. 0,31,0 +ffmsubs. 0,0,31 diff --git a/gas/testsuite/gas/ppc/ppc.exp b/gas/testsuite/gas/ppc/ppc.exp index 1a8a2bb263e..a41f5e961a1 100644 --- a/gas/testsuite/gas/ppc/ppc.exp +++ b/gas/testsuite/gas/ppc/ppc.exp @@ -175,3 +175,4 @@ run_dump_test "dsld" run_dump_test "dsrd" run_dump_test "maddedus" run_dump_test "minmax" +run_dump_test "ffmsubs" diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c index 63d44ed56f2..e76b83db120 100644 --- a/opcodes/ppc-opc.c +++ b/opcodes/ppc-opc.c @@ -9185,6 +9185,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { {"dmxvi8ger4", XX3(59,3), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, {"xvi8ger4", XX3(59,3), XX3ACC_MASK, POWER10, PPCVLE, {ACC, XA6a, XB6a}}, +{"ffmsubs", A(59,4,0), AFRC_MASK, SFFS, PPCVLE, {FRT, FRA, FRB}}, +{"ffmsubs.", A(59,4,1), AFRC_MASK, SFFS, PPCVLE, {FRT, FRA, FRB}}, + {"fdivs", A(59,18,0), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, {"fdivs.", A(59,18,1), AFRC_MASK, PPC, PPCEFS|PPCVLE, {FRT, FRA, FRB}}, -- 2.30.2