From 9c5067acf17a75524e2241486737ccb48fcf16ad Mon Sep 17 00:00:00 2001 From: Rhys Perry Date: Thu, 6 Dec 2018 14:57:40 +0000 Subject: [PATCH] ac/nir: implement 8-bit ssbo stores Signed-off-by: Rhys Perry Reviewed-by: Bas Nieuwenhuizen --- src/amd/common/ac_nir_to_llvm.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index c088537e1fd..5a199c1147d 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -1555,7 +1555,7 @@ static void visit_store_ssbo(struct ac_nir_context *ctx, LLVMValueRef rsrc = ctx->abi->load_ssbo(ctx->abi, get_src(ctx, instr->src[1]), true); - LLVMValueRef base_data = ac_to_float(&ctx->ac, src_data); + LLVMValueRef base_data = src_data; base_data = ac_trim_vector(&ctx->ac, base_data, instr->num_components); LLVMValueRef base_offset = get_src(ctx, instr->src[2]); @@ -1593,7 +1593,12 @@ static void visit_store_ssbo(struct ac_nir_context *ctx, offset = LLVMBuildAdd(ctx->ac.builder, base_offset, LLVMConstInt(ctx->ac.i32, start * elem_size_bytes, false), ""); - if (num_bytes == 2) { + if (num_bytes == 1) { + ac_build_tbuffer_store_byte(&ctx->ac, rsrc, data, + offset, ctx->ac.i32_0, + cache_policy & ac_glc, + writeonly_memory); + } else if (num_bytes == 2) { ac_build_tbuffer_store_short(&ctx->ac, rsrc, data, offset, ctx->ac.i32_0, cache_policy & ac_glc, -- 2.30.2