From 9c53c8c70568001942941c5e692eca0fd35b70c6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 6 May 2021 17:19:46 +0100 Subject: [PATCH] remove non-predicated svp64 ISACaller tests --- .../isa/test_caller_svp64_predication.py | 121 ------------------ 1 file changed, 121 deletions(-) diff --git a/src/openpower/decoder/isa/test_caller_svp64_predication.py b/src/openpower/decoder/isa/test_caller_svp64_predication.py index df55ca99..839b8a99 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_predication.py +++ b/src/openpower/decoder/isa/test_caller_svp64_predication.py @@ -181,127 +181,6 @@ class DecoderTestCase(FHDLTestCase): initial_cr=cr) self._check_regs(sim, expected_regs) - def tst_sv_add_2(self): - # adds: - # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 - # r1 is scalar so ENDS EARLY - isa = SVP64Asm(['sv.add 1, 5.v, 9.v' - ]) - lst = list(isa) - print ("listing", lst) - - # initial values in GPR regfile - initial_regs = [0] * 32 - initial_regs[9] = 0x1234 - initial_regs[10] = 0x1111 - initial_regs[5] = 0x4321 - initial_regs[6] = 0x2223 - # SVSTATE (in this case, VL=2) - svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) - # copy before running - expected_regs = deepcopy(initial_regs) - expected_regs[1] = 0x5555 - - with Program(lst, bigendian=False) as program: - sim = self.run_tst_program(program, initial_regs, svstate) - self._check_regs(sim, expected_regs) - - def tst_sv_add_3(self): - # adds: - # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234 - # 2 = 5 + 10 => 0x5432 = 0x4321+0x1111 - isa = SVP64Asm(['sv.add 1.v, 5, 9.v' - ]) - lst = list(isa) - print ("listing", lst) - - # initial values in GPR regfile - initial_regs = [0] * 32 - initial_regs[9] = 0x1234 - initial_regs[10] = 0x1111 - initial_regs[5] = 0x4321 - initial_regs[6] = 0x2223 - # SVSTATE (in this case, VL=2) - svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) - # copy before running - expected_regs = deepcopy(initial_regs) - expected_regs[1] = 0x5555 - expected_regs[2] = 0x5432 - - with Program(lst, bigendian=False) as program: - sim = self.run_tst_program(program, initial_regs, svstate) - self._check_regs(sim, expected_regs) - - def tst_sv_add_vl_0(self): - # adds: - # none because VL is zer0 - isa = SVP64Asm(['sv.add 1, 5.v, 9.v' - ]) - lst = list(isa) - print ("listing", lst) - - # initial values in GPR regfile - initial_regs = [0] * 32 - initial_regs[9] = 0x1234 - initial_regs[10] = 0x1111 - initial_regs[5] = 0x4321 - initial_regs[6] = 0x2223 - # SVSTATE (in this case, VL=0) - svstate = SVP64State() - svstate.vl[0:7] = 0 # VL - svstate.maxvl[0:7] = 0 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) - # copy before running - expected_regs = deepcopy(initial_regs) - - with Program(lst, bigendian=False) as program: - sim = self.run_tst_program(program, initial_regs, svstate) - self._check_regs(sim, expected_regs) - - def tst_sv_add_cr(self): - # adds when Rc=1: TODO CRs higher up - # 1 = 5 + 9 => 0 = -1+1 CR0=0b100 - # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111 CR1=0b010 - isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v' - ]) - lst = list(isa) - print ("listing", lst) - - # initial values in GPR regfile - initial_regs = [0] * 32 - initial_regs[9] = 0xffffffffffffffff - initial_regs[10] = 0x1111 - initial_regs[5] = 0x1 - initial_regs[6] = 0x2223 - # SVSTATE (in this case, VL=2) - svstate = SVP64State() - svstate.vl[0:7] = 2 # VL - svstate.maxvl[0:7] = 2 # MAXVL - print ("SVSTATE", bin(svstate.spr.asint())) - # copy before running - expected_regs = deepcopy(initial_regs) - expected_regs[1] = 0 - expected_regs[2] = 0x3334 - - with Program(lst, bigendian=False) as program: - sim = self.run_tst_program(program, initial_regs, svstate) - # XXX TODO, these need to move to higher range (offset) - cr0_idx = SVP64CROffs.CR0 - cr1_idx = SVP64CROffs.CR1 - CR0 = sim.crl[cr0_idx].get_range().value - CR1 = sim.crl[cr1_idx].get_range().value - print ("CR0", CR0) - print ("CR1", CR1) - self._check_regs(sim, expected_regs) - self.assertEqual(CR0, SelectableInt(2, 4)) - self.assertEqual(CR1, SelectableInt(4, 4)) - def test_intpred_vcompress(self): # reg num 0 1 2 3 4 5 6 7 8 9 10 11 # src r3=0b101 Y N Y -- 2.30.2