From 9c556e3c02a8b25fbcd764e019e3870d021684ec Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 2 Jul 2019 19:13:40 -0700
Subject: [PATCH] Add test

---
 tests/various/abc9.v  |  4 ++++
 tests/various/abc9.ys | 10 ++++++++++
 2 files changed, 14 insertions(+)

diff --git a/tests/various/abc9.v b/tests/various/abc9.v
index 8271cd249..a08b613a8 100644
--- a/tests/various/abc9.v
+++ b/tests/various/abc9.v
@@ -3,3 +3,7 @@ initial o = 1'b0;
 always @*
     o <= ~o;
 endmodule
+
+module abc9_test028(input i, output o);
+unknown u(~i, o);
+endmodule
diff --git a/tests/various/abc9.ys b/tests/various/abc9.ys
index 922f7005d..a84b637d9 100644
--- a/tests/various/abc9.ys
+++ b/tests/various/abc9.ys
@@ -1,4 +1,6 @@
 read_verilog abc9.v
+design -save read
+hierarchy -top abc9_test027
 proc
 design -save gold
 
@@ -12,3 +14,11 @@ design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
+design -load read
+hierarchy -top abc9_test028
+proc
+
+abc9 -lut 4
+select -assert-count 1 t:$lut r:LUT=1 r:WIDTH=1 %i %i
+select -assert-count 1 t:unknown
+select -assert-none t:$lut t:unknown %% t: %D
-- 
2.30.2