From 9c65658cfa1bd5b4f0023df19afbb113d27ecad0 Mon Sep 17 00:00:00 2001 From: Jacob Lifshay Date: Wed, 3 May 2023 18:08:46 -0700 Subject: [PATCH] comment fmin*/fmax* since they're being replaced with fminmax and to make space for fmv/fcvt --- openpower/isa/fptrans.mdwn | 1152 ++++++++++--------- openpower/isatables/RM-1P-2S1D.csv | 32 - openpower/isatables/minor_59.csv | 34 +- openpower/isatables/minor_63.csv | 34 +- src/openpower/decoder/power_enums.py | 35 +- src/openpower/test/fptrans/fptrans_cases.py | 66 +- 6 files changed, 697 insertions(+), 656 deletions(-) diff --git a/openpower/isa/fptrans.mdwn b/openpower/isa/fptrans.mdwn index 39a15350..e6799bb1 100644 --- a/openpower/isa/fptrans.mdwn +++ b/openpower/isa/fptrans.mdwn @@ -1442,581 +1442,583 @@ Special Registers Altered: VXSNAN VXISI VXIMZ CR1 (if Rc=1) -# [DRAFT] Floating MINNUM08 Single - -X-Form - -* fminnum08s FRT,FRA,FRB (Rc=0) -* fminnum08s. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_MINNUM08(SINGLE(FRA), SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MINNUM08 - -X-Form - -* fminnum08 FRT,FRA,FRB (Rc=0) -* fminnum08. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_MINNUM08(FRA, FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MAXNUM08 Single - -X-Form - -* fmaxnum08s FRT,FRA,FRB (Rc=0) -* fmaxnum08s. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_MAXNUM08(SINGLE(FRA), SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MAXNUM08 - -X-Form - -* fmaxnum08 FRT,FRA,FRB (Rc=0) -* fmaxnum08. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_MAXNUM08(FRA, FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MIN19 Single - -X-Form - -* fmin19s FRT,FRA,FRB (Rc=0) -* fmin19s. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_MIN19(SINGLE(FRA), SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MIN19 - -X-Form - -* fmin19 FRT,FRA,FRB (Rc=0) -* fmin19. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_MIN19(FRA, FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MAX19 Single - -X-Form - -* fmax19s FRT,FRA,FRB (Rc=0) -* fmax19s. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_MAX19(SINGLE(FRA), SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MAX19 - -X-Form - -* fmax19 FRT,FRA,FRB (Rc=0) -* fmax19. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_MAX19(FRA, FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MINNUM19 Single - -X-Form - -* fminnum19s FRT,FRA,FRB (Rc=0) -* fminnum19s. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_MINNUM19(SINGLE(FRA), SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MINNUM19 - -X-Form - -* fminnum19 FRT,FRA,FRB (Rc=0) -* fminnum19. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_MINNUM19(FRA, FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MAXNUM19 Single - -X-Form - -* fmaxnum19s FRT,FRA,FRB (Rc=0) -* fmaxnum19s. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_MAXNUM19(SINGLE(FRA), SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MAXNUM19 - -X-Form - -* fmaxnum19 FRT,FRA,FRB (Rc=0) -* fmaxnum19. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_MAXNUM19(FRA, FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MINC Single - -X-Form - -* fmincs FRT,FRA,FRB (Rc=0) -* fmincs. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_MINC(SINGLE(FRA), SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MINC - -X-Form - -* fminc FRT,FRA,FRB (Rc=0) -* fminc. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_MINC(FRA, FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MAXC Single - -X-Form - -* fmaxcs FRT,FRA,FRB (Rc=0) -* fmaxcs. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_MAXC(SINGLE(FRA), SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MAXC - -X-Form - -* fmaxc FRT,FRA,FRB (Rc=0) -* fmaxc. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_MAXC(FRA, FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MINMAGNUM08 Single - -X-Form - -* fminmagnum08s FRT,FRA,FRB (Rc=0) -* fminmagnum08s. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_MINMAGNUM08(SINGLE(FRA), SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MINMAGNUM08 - -X-Form - -* fminmagnum08 FRT,FRA,FRB (Rc=0) -* fminmagnum08. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_MINMAGNUM08(FRA, FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MAXMAGNUM08 Single - -X-Form - -* fmaxmagnum08s FRT,FRA,FRB (Rc=0) -* fmaxmagnum08s. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_MAXMAGNUM08(SINGLE(FRA), SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MAXMAGNUM08 - -X-Form - -* fmaxmagnum08 FRT,FRA,FRB (Rc=0) -* fmaxmagnum08. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_MAXMAGNUM08(FRA, FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MINMAG19 Single - -X-Form - -* fminmag19s FRT,FRA,FRB (Rc=0) -* fminmag19s. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_MINMAG19(SINGLE(FRA), SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MINMAG19 - -X-Form - -* fminmag19 FRT,FRA,FRB (Rc=0) -* fminmag19. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_MINMAG19(FRA, FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MAXMAG19 Single - -X-Form - -* fmaxmag19s FRT,FRA,FRB (Rc=0) -* fmaxmag19s. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_MAXMAG19(SINGLE(FRA), SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MAXMAG19 - -X-Form - -* fmaxmag19 FRT,FRA,FRB (Rc=0) -* fmaxmag19. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_MAXMAG19(FRA, FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MINMAGNUM19 Single - -X-Form - -* fminmagnum19s FRT,FRA,FRB (Rc=0) -* fminmagnum19s. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_MINMAGNUM19(SINGLE(FRA), SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MINMAGNUM19 - -X-Form - -* fminmagnum19 FRT,FRA,FRB (Rc=0) -* fminmagnum19. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_MINMAGNUM19(FRA, FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MAXMAGNUM19 Single - -X-Form - -* fmaxmagnum19s FRT,FRA,FRB (Rc=0) -* fmaxmagnum19s. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_MAXMAGNUM19(SINGLE(FRA), SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MAXMAGNUM19 - -X-Form - -* fmaxmagnum19 FRT,FRA,FRB (Rc=0) -* fmaxmagnum19. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_MAXMAGNUM19(FRA, FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MINMAGC Single - -X-Form - -* fminmagcs FRT,FRA,FRB (Rc=0) -* fminmagcs. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_MINMAGC(SINGLE(FRA), SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MINMAGC - -X-Form - -* fminmagc FRT,FRA,FRB (Rc=0) -* fminmagc. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_MINMAGC(FRA, FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MAXMAGC Single - -X-Form - -* fmaxmagcs FRT,FRA,FRB (Rc=0) -* fmaxmagcs. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- DOUBLE(bfp32_MAXMAGC(SINGLE(FRA), SINGLE(FRB))) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) - -# [DRAFT] Floating MAXMAGC - -X-Form - -* fmaxmagc FRT,FRA,FRB (Rc=0) -* fmaxmagc. FRT,FRA,FRB (Rc=1) - -Pseudo-code: - - FRT <- bfp64_MAXMAGC(FRA, FRB) - -Special Registers Altered: - - FPRF FR FI - FX OX UX XX - VXSNAN VXISI VXIMZ - CR1 (if Rc=1) + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + # [DRAFT] Floating MOD Single diff --git a/openpower/isatables/RM-1P-2S1D.csv b/openpower/isatables/RM-1P-2S1D.csv index f4c41521..4b91a4d2 100644 --- a/openpower/isatables/RM-1P-2S1D.csv +++ b/openpower/isatables/RM-1P-2S1D.csv @@ -99,29 +99,13 @@ fmuls,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRC,0,FRA,0,FRC,FRT,0,CR1,0 fatan2pis,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fatan2s,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fhypots,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fminnum08s,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fmin19s,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fminnum19s,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fmincs,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fmaxnum08s,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fmax19s,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fmaxnum19s,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fmaxcs,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fminmagnum08s,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fmaxmagnum08s,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fmods,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fpowns,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:RB,0,FRA,RB,0,FRT,0,CR1,0 frootns,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:RB,0,FRA,RB,0,FRT,0,CR1,0 -fminmag19s,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fmaxmag19s,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fminmagnum19s,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fmaxmagnum19s,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fremainders,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 ffadds,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fpowrs,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fpows,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fminmagcs,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fmaxmagcs,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fdiv,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fsub,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fadd,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 @@ -130,27 +114,11 @@ fmul,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRC,0,FRA,0,FRC,FRT,0,CR1,0 fatan2pi,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fatan2,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fhypot,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fminnum08,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fmin19,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fminnum19,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fminc,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fmaxnum08,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fmax19,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fmaxnum19,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fmaxc,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fminmagnum08,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fmaxmagnum08,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fmod,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fpown,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:RB,0,FRA,RB,0,FRT,0,CR1,0 frootn,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:RB,0,FRA,RB,0,FRT,0,CR1,0 -fminmag19,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fmaxmag19,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fminmagnum19,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fmaxmagnum19,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fremainder,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fpowr,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 fpow,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fminmagc,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 -fmaxmagc,NORMAL,,1P,EXTRA3,NO,d:FRT;d:CR1,s:FRA,s:FRB,0,FRA,FRB,0,FRT,0,CR1,0 rlwimi,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RA,s:RS,0,RA,0,RS,RA,0,CR0,0 rldimi,NORMAL,,1P,EXTRA3,NO,d:RA;d:CR0,s:RA,s:RS,0,RA,0,RS,RA,0,CR0,0 diff --git a/openpower/isatables/minor_59.csv b/openpower/isatables/minor_59.csv index 14fb4eb3..1df79976 100644 --- a/openpower/isatables/minor_59.csv +++ b/openpower/isatables/minor_59.csv @@ -60,21 +60,23 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 1010001111,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fasinhs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1010101110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,facoshs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1010101111,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fatanhs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1011001100,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminnum08s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1011101100,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxnum08s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1011001101,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmin19s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1011101101,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmax19s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1011001110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminnum19s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1011101110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxnum19s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1011001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmincs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1011101111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxcs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1100001110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminmagnum08s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1100001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxmagnum08s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1101101110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminmag19s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1101101111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxmag19s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1110001110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminmagnum19s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1110001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxmagnum19s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1111101110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminmagcs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1111101111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxmagcs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# fmin*s/fmax*s need to be removed https://bugs.libre-soc.org/show_bug.cgi?id=1057#c33 +# commented for now to make space for fmv/cvt +# 1011001100,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminnum08s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1011101100,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxnum08s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1011001101,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmin19s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1011101101,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmax19s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1011001110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminnum19s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1011101110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxnum19s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1011001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmincs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1011101111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxcs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1100001110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminmagnum08s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1100001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxmagnum08s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1101101110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminmag19s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1101101111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxmag19s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1110001110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminmagnum19s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1110001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxmagnum19s,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1111101110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminmagcs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1111101111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxmagcs,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1101001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmods,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1111001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fremainders,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/openpower/isatables/minor_63.csv b/openpower/isatables/minor_63.csv index 6f135770..0067705d 100644 --- a/openpower/isatables/minor_63.csv +++ b/openpower/isatables/minor_63.csv @@ -85,21 +85,23 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou 1010001111,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fasinh,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1010101110,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,facosh,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1010101111,FPU,OP_FPOP,NONE,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fatanh,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1011001100,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminnum08,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1011101100,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxnum08,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1011001101,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmin19,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1011101101,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmax19,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1011001110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminnum19,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1011101110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxnum19,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1011001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminc,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1011101111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxc,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1100001110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminmagnum08,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1100001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxmagnum08,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1101101110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminmag19,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1101101111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxmag19,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1110001110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminmagnum19,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1110001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxmagnum19,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1111101110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminmagc,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg -1111101111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxmagc,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# fmin*/fmax* need to be replaced with fminmax https://bugs.libre-soc.org/show_bug.cgi?id=1057 +# commented for now to make space for fmv/cvt +# 1011001100,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminnum08,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1011101100,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxnum08,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1011001101,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmin19,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1011101101,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmax19,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1011001110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminnum19,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1011101110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxnum19,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1011001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminc,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1011101111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxc,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1100001110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminmagnum08,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1100001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxmagnum08,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1101101110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminmag19,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1101101111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxmag19,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1110001110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminmagnum19,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1110001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxmagnum19,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1111101110,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fminmagc,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg +# 1111101111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmaxmagc,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1101001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fmod,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg 1111001111,FPU,OP_FPOP,FRA,FRB,NONE,FRT,NONE,CR1,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC_ONLY,0,0,fremainder,X,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index 399c1f46..e8406ccc 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -666,22 +666,25 @@ FPTRANS_INSNS = ( "fasinh", "fasinhs", "facosh", "facoshs", "fatanh", "fatanhs", - "fminnum08", "fminnum08s", - "fmaxnum08", "fmaxnum08s", - "fmin19", "fmin19s", - "fmax19", "fmax19s", - "fminnum19", "fminnum19s", - "fmaxnum19", "fmaxnum19s", - "fminc", "fmincs", - "fmaxc", "fmaxcs", - "fminmagnum08", "fminmagnum08s", - "fmaxmagnum08", "fmaxmagnum08s", - "fminmag19", "fminmag19s", - "fmaxmag19", "fmaxmag19s", - "fminmagnum19", "fminmagnum19s", - "fmaxmagnum19", "fmaxmagnum19s", - "fminmagc", "fminmagcs", - "fmaxmagc", "fmaxmagcs", + # fmin*/fmax* need to be replaced with fminmax + # https://bugs.libre-soc.org/show_bug.cgi?id=1057 + # commented for now to make space for fmv/cvt + # "fminnum08", "fminnum08s", + # "fmaxnum08", "fmaxnum08s", + # "fmin19", "fmin19s", + # "fmax19", "fmax19s", + # "fminnum19", "fminnum19s", + # "fmaxnum19", "fmaxnum19s", + # "fminc", "fmincs", + # "fmaxc", "fmaxcs", + # "fminmagnum08", "fminmagnum08s", + # "fmaxmagnum08", "fmaxmagnum08s", + # "fminmag19", "fminmag19s", + # "fmaxmag19", "fmaxmag19s", + # "fminmagnum19", "fminmagnum19s", + # "fmaxmagnum19", "fmaxmagnum19s", + # "fminmagc", "fminmagcs", + # "fmaxmagc", "fmaxmagcs", "fmod", "fmods", "fremainder", "fremainders", ) diff --git a/src/openpower/test/fptrans/fptrans_cases.py b/src/openpower/test/fptrans/fptrans_cases.py index f7e83bfe..57c5a735 100644 --- a/src/openpower/test/fptrans/fptrans_cases.py +++ b/src/openpower/test/fptrans/fptrans_cases.py @@ -1,4 +1,4 @@ -from openpower.test.common import TestAccumulatorBase +from openpower.test.common import TestAccumulatorBase, skip_case from openpower.sv.trans.svp64 import SVP64Asm from openpower.test.state import ExpectedState from openpower.simulator.program import Program @@ -1559,6 +1559,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminnum08s(self): lst = list(SVP64Asm(["fminnum08s 3,4,5"])) gprs = [0] * 32 @@ -1569,6 +1570,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminnum08s_(self): lst = list(SVP64Asm(["fminnum08s. 3,4,5"])) gprs = [0] * 32 @@ -1580,6 +1582,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminnum08(self): lst = list(SVP64Asm(["fminnum08 3,4,5"])) gprs = [0] * 32 @@ -1590,6 +1593,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminnum08_(self): lst = list(SVP64Asm(["fminnum08. 3,4,5"])) gprs = [0] * 32 @@ -1601,6 +1605,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxnum08s(self): lst = list(SVP64Asm(["fmaxnum08s 3,4,5"])) gprs = [0] * 32 @@ -1611,6 +1616,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxnum08s_(self): lst = list(SVP64Asm(["fmaxnum08s. 3,4,5"])) gprs = [0] * 32 @@ -1622,6 +1628,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxnum08(self): lst = list(SVP64Asm(["fmaxnum08 3,4,5"])) gprs = [0] * 32 @@ -1632,6 +1639,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxnum08_(self): lst = list(SVP64Asm(["fmaxnum08. 3,4,5"])) gprs = [0] * 32 @@ -1643,6 +1651,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmin19s(self): lst = list(SVP64Asm(["fmin19s 3,4,5"])) gprs = [0] * 32 @@ -1653,6 +1662,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmin19s_(self): lst = list(SVP64Asm(["fmin19s. 3,4,5"])) gprs = [0] * 32 @@ -1664,6 +1674,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmin19(self): lst = list(SVP64Asm(["fmin19 3,4,5"])) gprs = [0] * 32 @@ -1674,6 +1685,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmin19_(self): lst = list(SVP64Asm(["fmin19. 3,4,5"])) gprs = [0] * 32 @@ -1685,6 +1697,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmax19s(self): lst = list(SVP64Asm(["fmax19s 3,4,5"])) gprs = [0] * 32 @@ -1695,6 +1708,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmax19s_(self): lst = list(SVP64Asm(["fmax19s. 3,4,5"])) gprs = [0] * 32 @@ -1706,6 +1720,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmax19(self): lst = list(SVP64Asm(["fmax19 3,4,5"])) gprs = [0] * 32 @@ -1716,6 +1731,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmax19_(self): lst = list(SVP64Asm(["fmax19. 3,4,5"])) gprs = [0] * 32 @@ -1727,6 +1743,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminnum19s(self): lst = list(SVP64Asm(["fminnum19s 3,4,5"])) gprs = [0] * 32 @@ -1737,6 +1754,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminnum19s_(self): lst = list(SVP64Asm(["fminnum19s. 3,4,5"])) gprs = [0] * 32 @@ -1748,6 +1766,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminnum19(self): lst = list(SVP64Asm(["fminnum19 3,4,5"])) gprs = [0] * 32 @@ -1758,6 +1777,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminnum19_(self): lst = list(SVP64Asm(["fminnum19. 3,4,5"])) gprs = [0] * 32 @@ -1769,6 +1789,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxnum19s(self): lst = list(SVP64Asm(["fmaxnum19s 3,4,5"])) gprs = [0] * 32 @@ -1779,6 +1800,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxnum19s_(self): lst = list(SVP64Asm(["fmaxnum19s. 3,4,5"])) gprs = [0] * 32 @@ -1790,6 +1812,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxnum19(self): lst = list(SVP64Asm(["fmaxnum19 3,4,5"])) gprs = [0] * 32 @@ -1800,6 +1823,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxnum19_(self): lst = list(SVP64Asm(["fmaxnum19. 3,4,5"])) gprs = [0] * 32 @@ -1811,6 +1835,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmincs(self): lst = list(SVP64Asm(["fmincs 3,4,5"])) gprs = [0] * 32 @@ -1821,6 +1846,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmincs_(self): lst = list(SVP64Asm(["fmincs. 3,4,5"])) gprs = [0] * 32 @@ -1832,6 +1858,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminc(self): lst = list(SVP64Asm(["fminc 3,4,5"])) gprs = [0] * 32 @@ -1842,6 +1869,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminc_(self): lst = list(SVP64Asm(["fminc. 3,4,5"])) gprs = [0] * 32 @@ -1853,6 +1881,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxcs(self): lst = list(SVP64Asm(["fmaxcs 3,4,5"])) gprs = [0] * 32 @@ -1863,6 +1892,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxcs_(self): lst = list(SVP64Asm(["fmaxcs. 3,4,5"])) gprs = [0] * 32 @@ -1874,6 +1904,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxc(self): lst = list(SVP64Asm(["fmaxc 3,4,5"])) gprs = [0] * 32 @@ -1884,6 +1915,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxc_(self): lst = list(SVP64Asm(["fmaxc. 3,4,5"])) gprs = [0] * 32 @@ -1895,6 +1927,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminmagnum08s(self): lst = list(SVP64Asm(["fminmagnum08s 3,4,5"])) gprs = [0] * 32 @@ -1905,6 +1938,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminmagnum08s_(self): lst = list(SVP64Asm(["fminmagnum08s. 3,4,5"])) gprs = [0] * 32 @@ -1916,6 +1950,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminmagnum08(self): lst = list(SVP64Asm(["fminmagnum08 3,4,5"])) gprs = [0] * 32 @@ -1926,6 +1961,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminmagnum08_(self): lst = list(SVP64Asm(["fminmagnum08. 3,4,5"])) gprs = [0] * 32 @@ -1937,6 +1973,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxmagnum08s(self): lst = list(SVP64Asm(["fmaxmagnum08s 3,4,5"])) gprs = [0] * 32 @@ -1947,6 +1984,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxmagnum08s_(self): lst = list(SVP64Asm(["fmaxmagnum08s. 3,4,5"])) gprs = [0] * 32 @@ -1958,6 +1996,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxmagnum08(self): lst = list(SVP64Asm(["fmaxmagnum08 3,4,5"])) gprs = [0] * 32 @@ -1968,6 +2007,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxmagnum08_(self): lst = list(SVP64Asm(["fmaxmagnum08. 3,4,5"])) gprs = [0] * 32 @@ -1979,6 +2019,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminmag19s(self): lst = list(SVP64Asm(["fminmag19s 3,4,5"])) gprs = [0] * 32 @@ -1989,6 +2030,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminmag19s_(self): lst = list(SVP64Asm(["fminmag19s. 3,4,5"])) gprs = [0] * 32 @@ -2000,6 +2042,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminmag19(self): lst = list(SVP64Asm(["fminmag19 3,4,5"])) gprs = [0] * 32 @@ -2010,6 +2053,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminmag19_(self): lst = list(SVP64Asm(["fminmag19. 3,4,5"])) gprs = [0] * 32 @@ -2021,6 +2065,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxmag19s(self): lst = list(SVP64Asm(["fmaxmag19s 3,4,5"])) gprs = [0] * 32 @@ -2031,6 +2076,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxmag19s_(self): lst = list(SVP64Asm(["fmaxmag19s. 3,4,5"])) gprs = [0] * 32 @@ -2042,6 +2088,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxmag19(self): lst = list(SVP64Asm(["fmaxmag19 3,4,5"])) gprs = [0] * 32 @@ -2052,6 +2099,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxmag19_(self): lst = list(SVP64Asm(["fmaxmag19. 3,4,5"])) gprs = [0] * 32 @@ -2063,6 +2111,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminmagnum19s(self): lst = list(SVP64Asm(["fminmagnum19s 3,4,5"])) gprs = [0] * 32 @@ -2073,6 +2122,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminmagnum19s_(self): lst = list(SVP64Asm(["fminmagnum19s. 3,4,5"])) gprs = [0] * 32 @@ -2084,6 +2134,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminmagnum19(self): lst = list(SVP64Asm(["fminmagnum19 3,4,5"])) gprs = [0] * 32 @@ -2094,6 +2145,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminmagnum19_(self): lst = list(SVP64Asm(["fminmagnum19. 3,4,5"])) gprs = [0] * 32 @@ -2105,6 +2157,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxmagnum19s(self): lst = list(SVP64Asm(["fmaxmagnum19s 3,4,5"])) gprs = [0] * 32 @@ -2115,6 +2168,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxmagnum19s_(self): lst = list(SVP64Asm(["fmaxmagnum19s. 3,4,5"])) gprs = [0] * 32 @@ -2126,6 +2180,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxmagnum19(self): lst = list(SVP64Asm(["fmaxmagnum19 3,4,5"])) gprs = [0] * 32 @@ -2136,6 +2191,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxmagnum19_(self): lst = list(SVP64Asm(["fmaxmagnum19. 3,4,5"])) gprs = [0] * 32 @@ -2147,6 +2203,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminmagcs(self): lst = list(SVP64Asm(["fminmagcs 3,4,5"])) gprs = [0] * 32 @@ -2157,6 +2214,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminmagcs_(self): lst = list(SVP64Asm(["fminmagcs. 3,4,5"])) gprs = [0] * 32 @@ -2168,6 +2226,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminmagc(self): lst = list(SVP64Asm(["fminmagc 3,4,5"])) gprs = [0] * 32 @@ -2178,6 +2237,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fminmagc_(self): lst = list(SVP64Asm(["fminmagc. 3,4,5"])) gprs = [0] * 32 @@ -2189,6 +2249,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxmagcs(self): lst = list(SVP64Asm(["fmaxmagcs 3,4,5"])) gprs = [0] * 32 @@ -2199,6 +2260,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxmagcs_(self): lst = list(SVP64Asm(["fmaxmagcs. 3,4,5"])) gprs = [0] * 32 @@ -2210,6 +2272,7 @@ class FPTransCases(TestAccumulatorBase): e.crregs[1] = 0x4 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxmagc(self): lst = list(SVP64Asm(["fmaxmagc 3,4,5"])) gprs = [0] * 32 @@ -2220,6 +2283,7 @@ class FPTransCases(TestAccumulatorBase): e.fpregs[3] = 0x3ff0000000000000 self.add_case(Program(lst, False), gprs, fpregs=fprs, expected=e) + @skip_case("need to be updated to use fminmax") def case_fmaxmagc_(self): lst = list(SVP64Asm(["fmaxmagc. 3,4,5"])) gprs = [0] * 32 -- 2.30.2