From 9c66cea58fb5f89956a65d4b09655ad34949dd32 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 26 Jun 2020 20:47:16 +0100 Subject: [PATCH] add quick test showing Pi2LSUI not quite reading/writing to correct addresses --- src/soc/experiment/test/test_pi2ls.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/soc/experiment/test/test_pi2ls.py b/src/soc/experiment/test/test_pi2ls.py index 10e9b59e..33ab2cd4 100644 --- a/src/soc/experiment/test/test_pi2ls.py +++ b/src/soc/experiment/test/test_pi2ls.py @@ -66,7 +66,7 @@ def l0_cache_st(dut, addr, data, datalen): # yield from wait_busy(port1, False) # wait until not busy -def l0_cache_ld(dut, addr, datalen, expected): +def l0_cache_ld(dut, addr, datalen): if isinstance(dut.pi, Record): port1 = dut @@ -104,11 +104,15 @@ def l0_cache_ldst(arg, dut): #data = 0x4 yield from l0_cache_st(dut, 0x2, data, 2) yield from l0_cache_st(dut, 0x4, data2, 2) - result = yield from l0_cache_ld(dut, 0x2, 2, data) - result2 = yield from l0_cache_ld(dut, 0x4, 2, data2) + result = yield from l0_cache_ld(dut, 0x2, 2) + result2 = yield from l0_cache_ld(dut, 0x4, 2) arg.assertEqual(data, result, "data %x != %x" % (result, data)) arg.assertEqual(data2, result2, "data2 %x != %x" % (result2, data2)) + # now load both + data3 = data | (data2 << 16) + result3 = yield from l0_cache_ld(dut, 0x2, 4) + arg.assertEqual(data3, result3, "data3 %x != %x" % (result3, data3)) class TestPIMem(unittest.TestCase): -- 2.30.2