From 9c802850cf9e109873358ad6cb8fbf73938ef9d9 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Mon, 16 Sep 2019 09:40:00 +0100
Subject: [PATCH]

---
 simple_v_extension/vector_ops.mdwn | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/simple_v_extension/vector_ops.mdwn b/simple_v_extension/vector_ops.mdwn
index 11235f24e..edcd88ce7 100644
--- a/simple_v_extension/vector_ops.mdwn
+++ b/simple_v_extension/vector_ops.mdwn
@@ -99,3 +99,7 @@ Pseudocode:
 
         return (s0 * v0) + (s1 * v1);
     }
+
+# Expensive 3-operand OP32 operations
+
+3-operand operations are extremely expensive in terms of OP32 encoding space.  A potential idea is to embed 3 RVC register formats across two out of three 5-bit fields rs1/rs2/rd
-- 
2.30.2