From 9c8ee475047773d049beb3a18c5a3cc2a684dff6 Mon Sep 17 00:00:00 2001 From: lkcl Date: Wed, 22 Jun 2022 11:24:05 +0100 Subject: [PATCH] --- openpower/sv/vector_ops.mdwn | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn index cd6d492ef..c337395c4 100644 --- a/openpower/sv/vector_ops.mdwn +++ b/openpower/sv/vector_ops.mdwn @@ -12,7 +12,7 @@ Links: out of scope for this document [[openpower/sv/3d_vector_ops]] * [[simple_v_extension/specification/bitmanip]] previous version, contains pseudocode for sof, sif, sbf -* https://en.m.wikipedia.org/wiki/X86_Bit_manipulation_instruction_set#TBM_(Trailing_Bit_Manipulation) +* The core Power ISA was designed as scalar: SV provides a level of abstraction to add variable-length element-independent parallelism. Therefore there are not that many cases where *actual* Vector -- 2.30.2