From 9c93302df6f61d7c9c6ad128cd88ef8099b50c4e Mon Sep 17 00:00:00 2001
From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 29 Aug 2020 19:47:40 +0100
Subject: [PATCH] add XER read via DMI interface to sim.py

---
 src/soc/litex/florent/sim.py | 21 ++++++++++++++++++---
 src/soc/simple/issuer.py     |  2 +-
 2 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py
index b0fd474e..5dc3ec11 100755
--- a/src/soc/litex/florent/sim.py
+++ b/src/soc/litex/florent/sim.py
@@ -141,6 +141,7 @@ class LibreSoCSim(SoCSDRAM):
         pc = Signal(64)
         active_dbg = Signal()
         active_dbg_cr = Signal()
+        active_dbg_xer = Signal()
 
         # increment counter, Stop after 100000 cycles
         uptime = Signal(64)
@@ -219,7 +220,10 @@ class LibreSoCSim(SoCSDRAM):
              #   Display("    msr: %016x", dbg_dout),
              #),
              If(dbg_addr == 0b1000, # CR
-                Display("    cr: %016x", dbg_dout),
+                Display("    cr : %016x", dbg_dout),
+             ),
+             If(dbg_addr == 0b1001, # XER
+                Display("    xer: %016x", dbg_dout),
              ),
              If(dbg_addr == 0b101, # GPR
                 Display("    gpr: %016x", dbg_dout),
@@ -301,9 +305,20 @@ class LibreSoCSim(SoCSDRAM):
                 )
             )
 
+            #self.comb += active_dbg_xer.eq((0x10300 <= pc) & (pc <= 0x1094c))
+            self.comb += active_dbg_xer.eq(active_dbg_cr)
+
+            # get the CR
+            self.sync += If(active_dbg_xer & (dmicount == 20),
+                (dmi_addr.eq(0b1001), # XER
+                 dmi_req.eq(1),
+                 dmi_wen.eq(0),
+                )
+            )
+
         # read all 32 GPRs
         for i in range(32):
-            self.sync += If(active_dbg & (dmicount == 20+(i*8)),
+            self.sync += If(active_dbg & (dmicount == 24+(i*8)),
                 (dmi_addr.eq(0b100), # GSPR addr
                  dmi_din.eq(i), # r1
                  dmi_req.eq(1),
@@ -311,7 +326,7 @@ class LibreSoCSim(SoCSDRAM):
                 )
             )
 
-            self.sync += If(active_dbg & (dmicount == 24+(i*8)),
+            self.sync += If(active_dbg & (dmicount == 28+(i*8)),
                 (dmi_addr.eq(0b101), # GSPR data
                  dmi_req.eq(1),
                  dmi_wen.eq(0),
diff --git a/src/soc/simple/issuer.py b/src/soc/simple/issuer.py
index 5b4fade5..d1bcd7cd 100644
--- a/src/soc/simple/issuer.py
+++ b/src/soc/simple/issuer.py
@@ -277,7 +277,7 @@ class TestIssuer(Elaboratable):
 
         # aaand XER...
         with m.If(d_xer.req): # request for regfile access being made
-            comb += self.xer_r.ren.eq(0b111) # enable all
+            comb += self.xer_r.ren.eq(0b111111) # enable all
         d_xer_delay  = Signal()
         sync += d_xer_delay.eq(d_xer.req)
         with m.If(d_xer_delay):
-- 
2.30.2