From 9cced4f14c7f6309e57bab50d370f8754f6d3190 Mon Sep 17 00:00:00 2001 From: lkcl Date: Thu, 12 May 2022 12:39:10 +0100 Subject: [PATCH] --- openpower/sv/SimpleV_rationale.mdwn | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn index da962bb95..7b937d750 100644 --- a/openpower/sv/SimpleV_rationale.mdwn +++ b/openpower/sv/SimpleV_rationale.mdwn @@ -983,6 +983,20 @@ binaries, the size of each PE's TLB-aware L1 Cache needed would be miniscule compared to the average high-end CPU. +**Comparison of PE-CPU to GPU-CPU interaction** + +The informed reader will have noted the remarkable similarity between how +a CPU communicates with a GPU to schedule tasks, and the proposed +architecture. CPUs schedule tasks as follows: + +* User-space program encounters an OpenGL function, in the + CPU's ISA. +* Proprietary GPU Driver, still in the CPU's ISA, prepares a + Shader Binary written in the GPU's ISA. +* GPU Driver wishes to transfer both the data and the Shader Binary + to the GPU. Both may only do so via Shared Memory, usually + DMA over PCIe. + **Roadmap summary of Advanced SVP64** The future direction for SVP64, then, is: -- 2.30.2