From 9d101af76bd69deba8210610124973b1ac6e0573 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 10 Jun 2020 13:18:08 +0100 Subject: [PATCH] code-morph regspecmap functions, split into separate read/write --- src/soc/decoder/power_decoder2.py | 18 +++- src/soc/decoder/power_regspec_map.py | 145 ++++++++++++++++++--------- src/soc/simple/core.py | 7 +- 3 files changed, 117 insertions(+), 53 deletions(-) diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 9ff553fa..26a8f634 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -9,7 +9,8 @@ from nmigen.cli import rtlil from nmutil.iocontrol import RecordObject from nmutil.extend import exts -from soc.decoder.power_regspec_map import regspec_decode +from soc.decoder.power_regspec_map import regspec_decode_read +from soc.decoder.power_regspec_map import regspec_decode_write from soc.decoder.power_decoder import create_pdecode from soc.decoder.power_enums import (InternalOp, CryIn, Function, CRInSel, CROutSel, @@ -663,18 +664,25 @@ class PowerDecode2(Elaboratable): comb += e.trapaddr.eq(0x70) # addr=0x700 (strip first nibble) return m - def regspecmap(self, regfile, regname): - """regspecmap: provides PowerDecode2 with an encoding relationship + def regspecmap_read(self, regfile, regname): + """regspecmap_read: provides PowerDecode2 with an encoding relationship to Function Unit port regfiles (read-enable, read regnum, write regnum) regfile and regname arguments are fields 1 and 2 from a given regspec. """ - return regspec_decode(self.e, regfile, regname) + return regspec_decode_read(self.e, regfile, regname) + + def regspecmap_write(self, regfile, regname): + """regspecmap_write: provides PowerDecode2 with an encoding relationship + to Function Unit port regfiles (write port, write regnum) + regfile and regname arguments are fields 1 and 2 from a given regspec. + """ + return regspec_decode_write(self.e, regfile, regname) def rdflags(self, cu): rdl = [] for idx in range(cu.n_src): regfile, regname, _ = cu.get_in_spec(idx) - rdflag, read, write = self.regspecmap(regfile, regname) + rdflag, read = self.regspecmap_read(regfile, regname) rdl.append(rdflag) print ("rdflags", rdl) return Cat(*rdl) diff --git a/src/soc/decoder/power_regspec_map.py b/src/soc/decoder/power_regspec_map.py index 4b01a1ca..fdc9c323 100644 --- a/src/soc/decoder/power_regspec_map.py +++ b/src/soc/decoder/power_regspec_map.py @@ -1,7 +1,34 @@ """regspec_decode -function for the relationship between regspecs and Decode2Execute1Type +functions for the relationship between regspecs and Decode2Execute1Type +these functions encodes the understanding (relationship) between +Regfiles, Computation Units, and the Power ISA Decoder (PowerDecoder2). + +based on the regspec, which contains the register file name and register +name, return a tuple of: + +* how the decoder should determine whether the Function Unit needs + access to a given Regport or not +* which Regfile number on that port should be read to get that data +* when it comes to writing: likewise, which Regfile num should be written + +Note that some of the port numbering encoding is *unary*. in the case +of "Full Condition Register", it's a full 8-bit mask of read/write-enables. +This actually matches directly with the XFX field in MTCR, and at +some point that 8-bit mask from the instruction could actually be passed directly through to full_cr (TODO). + +For the INT and CR numbering, these are expressed in binary in the +instruction (note however that XFX in MTCR is unary-masked!) + +XER is implicitly-encoded based on whether the operation has carry or +overflow. + +FAST regfile is, again, implicitly encoded, back in PowerDecode2, based +on the type of operation (see DecodeB for an example). + +The SPR regfile on the other hand is *binary*-encoded, and, furthermore, +has to be "remapped". see https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs """ from nmigen import Const @@ -9,62 +36,85 @@ from soc.regfile.regfiles import XERRegs, FastRegs from soc.decoder.power_enums import CryIn -def regspec_decode(e, regfile, name): - """regspec_decode - - this function encodes the understanding (relationship) between - Regfiles, Computation Units, and the Power ISA Decoder (PowerDecoder2). +def regspec_decode_read(e, regfile, name): + """regspec_decode_read + """ - based on the regspec, which contains the register file name and register - name, return a tuple of: + if regfile == 'INT': + # Int register numbering is *unary* encoded + if name == 'ra': # RA + return e.read_reg1.ok, 1<