From 9d1443c1a8fe5b13d53f23b8165c423f3e6d629a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 13 May 2020 09:31:20 +0200 Subject: [PATCH] cpu/soc_core: automatically set csr mapping to 0x00000000 when using CPUNone, remove csr_base parameter that was used for that. --- litex/soc/cores/cpu/__init__.py | 1 + litex/soc/integration/soc_core.py | 3 +-- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/cores/cpu/__init__.py b/litex/soc/cores/cpu/__init__.py index 4c273e50..d861bf07 100644 --- a/litex/soc/cores/cpu/__init__.py +++ b/litex/soc/cores/cpu/__init__.py @@ -28,6 +28,7 @@ class CPUNone(CPU): io_regions = {0x00000000: 0x100000000} # origin, length periph_buses = [] memory_buses = [] + mem_map = {"csr": 0x00000000} CPU_GCC_TRIPLE_RISCV32 = ( "riscv64-unknown-elf", diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 8a4dd937..a44f6d8f 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -85,7 +85,6 @@ class SoCCore(LiteXSoC): csr_alignment = 32, csr_address_width = 14, csr_paging = 0x800, - csr_base = None, # Identifier parameters ident = "", ident_version = False, @@ -185,7 +184,7 @@ class SoCCore(LiteXSoC): self.add_timer(name="timer0") # Add CSR bridge - self.add_csr_bridge(self.mem_map["csr"] if csr_base is None else csr_base) + self.add_csr_bridge(self.mem_map["csr"]) # Methods -------------------------------------------------------------------------------------- -- 2.30.2