From 9d170b09442f1f5947b7a024639339397bcab6b0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 28 Jun 2019 23:27:23 +0200 Subject: [PATCH] soc_core: rearrange default mem_map --- litex/soc/integration/soc_core.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index a6592044..877d00a4 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -134,9 +134,9 @@ class SoCCore(Module): interrupt_map = {} mem_map = { "rom": 0x00000000, # (default shadow @0x80000000) - "sram": 0x10000000, # (default shadow @0x90000000) + "sram": 0x01000000, # (default shadow @0x81000000) + "csr": 0x02000000, # (default shadow @0x82000000) "main_ram": 0x40000000, # (default shadow @0xc0000000) - "csr": 0x60000000, # (default shadow @0xe0000000) } def __init__(self, platform, clk_freq, # CPU parameters -- 2.30.2