From 9d241f8cd3409c959eb25de83fb5cbb1a3334788 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Robert=20J=C3=B6rdens?= Date: Sat, 29 Jun 2013 21:25:06 -0600 Subject: [PATCH] coding.py: rewrite If() to make verilog more readable --- migen/genlib/coding.py | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/migen/genlib/coding.py b/migen/genlib/coding.py index 559dab05..ed60e2f3 100644 --- a/migen/genlib/coding.py +++ b/migen/genlib/coding.py @@ -22,10 +22,8 @@ class PriorityEncoder(Module): self.i = Signal(width) # one-hot, lsb has priority self.o = Signal(max=width) # binary self.n = Signal() # none - act = If(0) - for j in range(width): - act = act.Elif(self.i[j], self.o.eq(j)) - self.comb += act + for j in range(width)[::-1]: # last has priority + self.comb += If(self.i[j], self.o.eq(j)) self.comb += self.n.eq(self.i == 0) class Decoder(Module): @@ -41,9 +39,7 @@ class PriorityDecoder(Decoder): pass # same def _main(): - from migen.sim.generic import Simulator, TopLevel from migen.fhdl import verilog - e = Encoder(8) print(verilog.convert(e, ios={e.i, e.o, e.n})) pe = PriorityEncoder(8) -- 2.30.2