From 9d2a33a36a794ad982857f0a436284690746c905 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 8 Oct 2022 12:45:30 +0100 Subject: [PATCH] convert TargetAddrOperand to base class EXTSOperand (about to do DQ/DS operand) --- src/openpower/decoder/power_insn.py | 54 ++++++++++++----------- src/openpower/sv/trans/test_pysvp64dis.py | 7 +++ 2 files changed, 36 insertions(+), 25 deletions(-) diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py index 4345ac41..64b9ea32 100644 --- a/src/openpower/decoder/power_insn.py +++ b/src/openpower/decoder/power_insn.py @@ -747,45 +747,49 @@ class CR5Operand(RegisterOperand): return (value, span) -class TargetAddrOperand(RegisterOperand): - def disassemble(self, insn, record, field, - verbosity=Verbosity.NORMAL, indent=""): +class EXTSOperand(RegisterOperand): + n_zeros: int # number of zeros - set through constructor override + d_field: str # field name to report - ditto + + def span(self, record): + return record.fields[self.d_field] + + def disassemble(self, insn, record, verbosity=Verbosity.NORMAL, indent=""): span = self.span(record=record) if isinstance(insn, SVP64Instruction): span = tuple(map(lambda bit: (bit + 32), span)) value = insn[span] if verbosity >= Verbosity.VERBOSE: - span = (tuple(map(str, span)) + ("{0}", "{0}")) - yield f"{indent}{self.name} = EXTS({field} || 0b00))" - yield f"{indent}{indent}{field}" - yield f"{indent}{indent}{indent}{int(value):0{value.bits}b}00" - yield f"{indent}{indent}{indent}{', '.join(span)}" + span = (tuple(map(str, span)) + ("{0}",)*self.n_zeros) + z = "0" * self.n_zeros + yield indent + "%s = EXTS(%s || 0b%s)" % (self.name, self.d_field, z) + yield indent * 2 + self.d_field + yield indent * 3 + f"{int(value):0{value.bits}b}00" + yield indent * 3 + ', '.join(span) else: yield hex(_selectconcat(value, - _SelectableInt(value=0b00, bits=2)).to_signed_int()) + _SelectableInt(value=0, bits=self.n_zeros)).to_signed_int()) -class TargetAddrOperandLI(TargetAddrOperand): - def span(self, record): - return record.fields["LI"] +class TargetAddrOperand(EXTSOperand): + """set up TargetAddrOperand as an EXTSOperand with 2 leading zeros + """ + def __init__(self, *args, **kwargs): # no idea what the args are + self.n_zeros = 2 + super().__init__(*args, **kwargs) - def disassemble(self, insn, record, - verbosity=Verbosity.NORMAL, indent=""): - return super().disassemble(field="LI", - insn=insn, record=record, - verbosity=verbosity, indent=indent) +class TargetAddrOperandLI(TargetAddrOperand): + def __init__(self, *args, **kwargs): # no idea what the args are + self.d_field = 'LI' + super().__init__(*args, **kwargs) -class TargetAddrOperandBD(TargetAddrOperand): - def span(self, record): - return record.fields["BD"] - def disassemble(self, insn, record, - verbosity=Verbosity.NORMAL, indent=""): - return super().disassemble(field="BD", - insn=insn, record=record, - verbosity=verbosity, indent=indent) +class TargetAddrOperandBD(TargetAddrOperand): + def __init__(self, *args, **kwargs): # no idea what the args are + self.d_field = 'BD' + super().__init__(*args, **kwargs) class DOperandDX(SignedOperand): diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py index 107f60ff..40a18cc1 100644 --- a/src/openpower/sv/trans/test_pysvp64dis.py +++ b/src/openpower/sv/trans/test_pysvp64dis.py @@ -346,6 +346,13 @@ class SVSTATETestCase(unittest.TestCase): ] self._do_tst(expected) + def test_24_bc(self): + expected = [ + "b 0x28", + "bc 16,0,-0xb4", + ] + self._do_tst(expected) + if __name__ == "__main__": unittest.main() -- 2.30.2