From 9d42a4fe3b06697ac0d17b7399cbb011106dacbf Mon Sep 17 00:00:00 2001 From: Jean THOMAS Date: Fri, 17 Jul 2020 18:46:14 +0200 Subject: [PATCH] Use XDR for RAS#, CAS#, WE#, CLK_EN and ODT --- gram/phy/ecp5ddrphy.py | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py index 139b40e..9f09bac 100644 --- a/gram/phy/ecp5ddrphy.py +++ b/gram/phy/ecp5ddrphy.py @@ -204,17 +204,17 @@ class ECP5DDRPHY(Peripheral, Elaboratable): if hasattr(self.pads, "cs_n"): controls.append("cs_n") for name in controls: - for i in range(len(getattr(self.pads, name))): - m.submodules += Instance("ODDRX2F", - i_RST=ResetSignal("dramsync"), - i_ECLK=ClockSignal("sync2x"), - i_SCLK=ClockSignal(), - i_D0=getattr(dfi.phases[0], name)[i], - i_D1=getattr(dfi.phases[0], name)[i], - i_D2=getattr(dfi.phases[1], name)[i], - i_D3=getattr(dfi.phases[1], name)[i], - o_Q=getattr(self.pads, name).o[i] - ) + m.d.comb += [ + getattr(self.pads, name).o_clk.eq(ClockSignal("dramsync")), + getattr(self.pads, name).o_fclk.eq(ClockSignal("sync2x")), + ] + for i in range(len(getattr(self.pads, name).o0)): + m.d.comb += [ + getattr(self.pads, name).o0[i].eq(getattr(dfi.phases[0], name)[i]), + getattr(self.pads, name).o1[i].eq(getattr(dfi.phases[0], name)[i]), + getattr(self.pads, name).o2[i].eq(getattr(dfi.phases[1], name)[i]), + getattr(self.pads, name).o3[i].eq(getattr(dfi.phases[1], name)[i]), + ] # DQ --------------------------------------------------------------------------------------- dq_oe = Signal() -- 2.30.2