From 9d4a42e8c5fd2409922250f63a788a38bdfc2c46 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Tue, 31 May 2016 12:14:37 +0100 Subject: [PATCH] arm: Correctly check translation mode (aarch64/aarch32) According to the ARM ARM (see AArch32.TranslateAddress in the pseudocode library), the TLB should be operating in aarch64 mode if the EL0 is aarch32 and EL1 is aarch64. This is currently not the case in gem5, which breaks 64/32 interprocessing. Update the check to match the reference manual. Change-Id: I6f1444d57c0e2eb5f8880f513f33a9197b7cb2ce Signed-off-by: Andreas Sandberg Reviewed-by: Mitch Hayenga Reviewed-by: Nikos Nikoleris --- src/arch/arm/tlb.cc | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 3fc317048..1f6910262 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -1197,11 +1197,15 @@ TLB::updateMiscReg(ThreadContext *tc, ArmTranslationType tranType) DPRINTF(TLBVerbose, "TLB variables changed!\n"); cpsr = tc->readMiscReg(MISCREG_CPSR); + // Dependencies: SCR/SCR_EL3, CPSR - isSecure = inSecureState(tc); - isSecure &= (tranType & HypMode) == 0; - isSecure &= (tranType & S1S2NsTran) == 0; - aarch64 = !cpsr.width; + isSecure = inSecureState(tc) && + !(tranType & HypMode) && !(tranType & S1S2NsTran); + + const OperatingMode op_mode = (OperatingMode) (uint8_t)cpsr.mode; + aarch64 = opModeIs64(op_mode) || + (opModeToEL(op_mode) == EL0 && ELIs64(tc, EL1)); + if (aarch64) { // AArch64 aarch64EL = (ExceptionLevel) (uint8_t) cpsr.el; switch (aarch64EL) { -- 2.30.2