From 9d52e551a5874e54bc80f306bf3cacbad2441315 Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Mon, 1 Sep 2014 10:48:09 -0400 Subject: [PATCH] nv50: mt address may not be the underlying bo's start address With VP2, nv50_miptree is faked because the underlying bo's have to be laid out in a certain way. This is done by adjusting the address. Make sure that blits (and everything else for consistency) use the mt address rather than the bo address as a base. This fixes retrieving chroma plane with VDPAU. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82255 Tested-by: Emil Velikov Signed-off-by: Ilia Mirkin Cc: "10.2 10.3" --- .../drivers/nouveau/nv50/nv50_state_validate.c | 8 ++++---- src/gallium/drivers/nouveau/nv50/nv50_surface.c | 16 ++++++++-------- src/gallium/drivers/nouveau/nv50/nv50_transfer.c | 2 ++ 3 files changed, 14 insertions(+), 12 deletions(-) diff --git a/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c index 1dcb961ce39..4f2758af499 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_state_validate.c @@ -54,8 +54,8 @@ nv50_validate_fb(struct nv50_context *nv50) assert(mt->layout_3d || !array_mode || array_size == 1); BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(i)), 5); - PUSH_DATAh(push, bo->offset + sf->offset); - PUSH_DATA (push, bo->offset + sf->offset); + PUSH_DATAh(push, mt->base.address + sf->offset); + PUSH_DATA (push, mt->base.address + sf->offset); PUSH_DATA (push, nv50_format_table[sf->base.format].rt); if (likely(nouveau_bo_memtype(bo))) { PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode); @@ -97,8 +97,8 @@ nv50_validate_fb(struct nv50_context *nv50) int unk = mt->base.base.target == PIPE_TEXTURE_3D || sf->depth == 1; BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5); - PUSH_DATAh(push, bo->offset + sf->offset); - PUSH_DATA (push, bo->offset + sf->offset); + PUSH_DATAh(push, mt->base.address + sf->offset); + PUSH_DATA (push, mt->base.address + sf->offset); PUSH_DATA (push, nv50_format_table[fb->zsbuf->format].rt); PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode); PUSH_DATA (push, mt->layer_stride >> 2); diff --git a/src/gallium/drivers/nouveau/nv50/nv50_surface.c b/src/gallium/drivers/nouveau/nv50/nv50_surface.c index 600f4f93b48..8ec4a5fc161 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_surface.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_surface.c @@ -114,8 +114,8 @@ nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst, PUSH_DATA (push, mt->level[level].pitch); PUSH_DATA (push, width); PUSH_DATA (push, height); - PUSH_DATAh(push, bo->offset + offset); - PUSH_DATA (push, bo->offset + offset); + PUSH_DATAh(push, mt->base.address + offset); + PUSH_DATA (push, mt->base.address + offset); } else { BEGIN_NV04(push, SUBC_2D(mthd), 5); PUSH_DATA (push, format); @@ -126,8 +126,8 @@ nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst, BEGIN_NV04(push, SUBC_2D(mthd + 0x18), 4); PUSH_DATA (push, width); PUSH_DATA (push, height); - PUSH_DATAh(push, bo->offset + offset); - PUSH_DATA (push, bo->offset + offset); + PUSH_DATAh(push, mt->base.address + offset); + PUSH_DATA (push, mt->base.address + offset); } #if 0 @@ -299,8 +299,8 @@ nv50_clear_render_target(struct pipe_context *pipe, BEGIN_NV04(push, NV50_3D(RT_CONTROL), 1); PUSH_DATA (push, 1); BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(0)), 5); - PUSH_DATAh(push, bo->offset + sf->offset); - PUSH_DATA (push, bo->offset + sf->offset); + PUSH_DATAh(push, mt->base.address + sf->offset); + PUSH_DATA (push, mt->base.address + sf->offset); PUSH_DATA (push, nv50_format_table[dst->format].rt); PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode); PUSH_DATA (push, mt->layer_stride >> 2); @@ -381,8 +381,8 @@ nv50_clear_depth_stencil(struct pipe_context *pipe, nv50->scissors_dirty |= 1; BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5); - PUSH_DATAh(push, bo->offset + sf->offset); - PUSH_DATA (push, bo->offset + sf->offset); + PUSH_DATAh(push, mt->base.address + sf->offset); + PUSH_DATA (push, mt->base.address + sf->offset); PUSH_DATA (push, nv50_format_table[dst->format].rt); PUSH_DATA (push, mt->level[sf->base.u.tex.level].tile_mode); PUSH_DATA (push, mt->layer_stride >> 2); diff --git a/src/gallium/drivers/nouveau/nv50/nv50_transfer.c b/src/gallium/drivers/nouveau/nv50/nv50_transfer.c index f71605281b6..fc6b24aac28 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_transfer.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_transfer.c @@ -24,6 +24,8 @@ nv50_m2mf_rect_setup(struct nv50_m2mf_rect *rect, rect->bo = mt->base.bo; rect->domain = mt->base.domain; rect->base = mt->level[l].offset; + if (mt->base.bo->offset != mt->base.address) + rect->base += mt->base.address - mt->base.bo->offset; rect->pitch = mt->level[l].pitch; if (util_format_is_plain(res->format)) { rect->width = w << mt->ms_x; -- 2.30.2