From 9d681a7a18880cc10e2c19afc6e0624331d67d25 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Wed, 21 Jun 2017 17:48:14 +0100 Subject: [PATCH] i965: perf: use new subslices numbers from device info Signed-off-by: Lionel Landwerlin Reviewed-by: Ben Widawsky --- .../drivers/dri/i965/brw_performance_query.c | 49 +++++++------------ 1 file changed, 17 insertions(+), 32 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c b/src/mesa/drivers/dri/i965/brw_performance_query.c index 57feae7245f..d7902de836c 100644 --- a/src/mesa/drivers/dri/i965/brw_performance_query.c +++ b/src/mesa/drivers/dri/i965/brw_performance_query.c @@ -1826,26 +1826,25 @@ init_oa_sys_vars(struct brw_context *brw, const char *sysfs_dev_dir) brw->perfquery.sys_vars.gt_min_freq = min_freq_mhz * 1000000; brw->perfquery.sys_vars.gt_max_freq = max_freq_mhz * 1000000; brw->perfquery.sys_vars.timestamp_frequency = devinfo->timestamp_frequency; + brw->perfquery.sys_vars.n_eu_slices = devinfo->num_slices; + /* Assuming uniform distribution of subslices per slices. */ + brw->perfquery.sys_vars.n_eu_sub_slices = devinfo->num_subslices[0]; if (devinfo->is_haswell) { + brw->perfquery.sys_vars.slice_mask = 0; + brw->perfquery.sys_vars.subslice_mask = 0; + + for (int s = 0; s < devinfo->num_slices; s++) + brw->perfquery.sys_vars.slice_mask |= 1U << s; + for (int ss = 0; ss < devinfo->num_subslices[0]; ss++) + brw->perfquery.sys_vars.subslice_mask |= 1U << ss; + if (devinfo->gt == 1) { brw->perfquery.sys_vars.n_eus = 10; - brw->perfquery.sys_vars.n_eu_slices = 1; - brw->perfquery.sys_vars.n_eu_sub_slices = 1; - brw->perfquery.sys_vars.slice_mask = 0x1; - brw->perfquery.sys_vars.subslice_mask = 0x1; } else if (devinfo->gt == 2) { brw->perfquery.sys_vars.n_eus = 20; - brw->perfquery.sys_vars.n_eu_slices = 1; - brw->perfquery.sys_vars.n_eu_sub_slices = 2; - brw->perfquery.sys_vars.slice_mask = 0x1; - brw->perfquery.sys_vars.subslice_mask = 0x3; } else if (devinfo->gt == 3) { brw->perfquery.sys_vars.n_eus = 40; - brw->perfquery.sys_vars.n_eu_slices = 2; - brw->perfquery.sys_vars.n_eu_sub_slices = 2; - brw->perfquery.sys_vars.slice_mask = 0x3; - brw->perfquery.sys_vars.subslice_mask = 0xf; } else unreachable("not reached"); } else { @@ -1854,29 +1853,15 @@ init_oa_sys_vars(struct brw_context *brw, const char *sysfs_dev_dir) int ret; int slice_mask = 0; int ss_mask = 0; - int s_max = devinfo->num_slices; /* maximum number of slices */ - int ss_max = 0; /* maximum number of subslices per slice */ + /* maximum number of slices */ + int s_max = devinfo->num_slices; + /* maximum number of subslices per slice (assuming uniform subslices per + * slices) + */ + int ss_max = devinfo->num_subslices[0]; uint64_t subslice_mask = 0; int s; - if (devinfo->gen == 8) { - if (devinfo->gt == 1) { - ss_max = 2; - } else { - ss_max = 3; - } - } else if (devinfo->gen == 9) { - /* XXX: beware that the kernel (as of writing) actually works as if - * ss_max == 4 since the HW register that reports the global subslice - * mask has 4 bits while in practice the limit is 3. It's also - * important that we initialize $SubsliceMask with 3 bits per slice - * since that's what the counter availability expressions in XML - * expect. - */ - ss_max = 3; - } else - return false; - gp.param = I915_PARAM_SLICE_MASK; gp.value = &slice_mask; ret = drmIoctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp); -- 2.30.2