From 9d823c9093bfa4be27a18225462753ce0fd76bbf Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Wed, 19 Jan 2022 18:38:48 +0000 Subject: [PATCH] trap types memory exception (TT.MEMEXC) instead of TT.PRIV which stops SRR1 bit 45 being set by mistake --- src/openpower/decoder/power_decoder2.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index d7154e17..a0e87d19 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -1538,18 +1538,18 @@ class PowerDecode2(PowerDecodeSubset): # after a failed LD/ST. with m.Elif(ldst_exc.happened): with m.If(ldst_exc.alignment): - self.trap(m, TT.PRIV, 0x600) + self.trap(m, TT.MEMEXC, 0x600) with m.Elif(ldst_exc.instr_fault): with m.If(ldst_exc.segment_fault): - self.trap(m, TT.PRIV, 0x480) + self.trap(m, TT.MEMEXC, 0x480) with m.Else(): # pass exception info to trap to create SRR1 self.trap(m, TT.MEMEXC, 0x400, ldst_exc) with m.Else(): with m.If(ldst_exc.segment_fault): - self.trap(m, TT.PRIV, 0x380) + self.trap(m, TT.MEMEXC, 0x380) with m.Else(): - self.trap(m, TT.PRIV, 0x300) + self.trap(m, TT.MEMEXC, 0x300) # decrement counter (v3.0B p1099): TODO 32-bit version (MSR.LPCR) with m.Elif(dec_irq_ok): -- 2.30.2