From 9d9782084a3dc37ed9247e26565cf732de61b265 Mon Sep 17 00:00:00 2001 From: lkcl Date: Mon, 8 May 2023 17:48:51 +0100 Subject: [PATCH] spelling --- openpower/sv/svp64.mdwn | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index c159e0fc6..5b584079c 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -998,7 +998,7 @@ they are different SV regs. * `rlwimi RA, RS, ...` * Rsrc1_EXTRA3 applies to RS as the first src -* Rsrc2_EXTRA3 applies to RA as the secomd src +* Rsrc2_EXTRA3 applies to RA as the second src * Rdest_EXTRA3 applies to RA to create an **independent** dest. With the addition of the EXTRA bits, the three registers @@ -1034,7 +1034,7 @@ single-predicate, three registers (2 read, 1 write) ### RM-2P-2S1D/1S2D/3S The primary purpose for this encoding is for Twin Predication on LOAD -and STORE operations. see [[sv/ldst]] for detailed anslysis. +and STORE operations. see [[sv/ldst]] for detailed analysis. **RM-2P-2S1D:** -- 2.30.2