From 9da28c4ea51c466ca6c19747877d9de2b0704ad7 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 16 Dec 2019 11:12:38 +0100 Subject: [PATCH] build/xilinx/XilinxMultiRegImpl: fix n=0 case --- litex/build/xilinx/common.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex/build/xilinx/common.py b/litex/build/xilinx/common.py index dffe5872..8848d85c 100644 --- a/litex/build/xilinx/common.py +++ b/litex/build/xilinx/common.py @@ -78,7 +78,8 @@ class XilinxMultiRegImpl(MultiRegImpl): if not hasattr(i, "attr"): i0, i = i, Signal() self.comb += i.eq(i0) - self.regs[0].attr.add("mr_ff") + if len(self.regs): + self.regs[0].attr.add("mr_ff") for r in self.regs: r.attr.add("async_reg") r.attr.add("no_shreg_extract") -- 2.30.2