From 9dbaa7f67d3e3b3c48db5dc6ea91be57f91ff496 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 5 Sep 2020 00:48:08 +0100 Subject: [PATCH] reduce CSR data width to 8 as an experiment --- src/soc/litex/florent/sim.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/litex/florent/sim.py b/src/soc/litex/florent/sim.py index 475314f2..460a85d5 100755 --- a/src/soc/litex/florent/sim.py +++ b/src/soc/litex/florent/sim.py @@ -96,7 +96,7 @@ class LibreSoCSim(SoCSDRAM): #bus_data_width = 64, csr_address_width = 12, # limit to 0x4000 cpu_variant = variant, - csr_data_width = 32, + csr_data_width = 8, l2_size = 0, uart_name = "sim", with_sdram = with_sdram, -- 2.30.2