From 9ddb1162f1f686d1c8d1ccdc7c3c6b97d9e8241d Mon Sep 17 00:00:00 2001 From: lkcl Date: Fri, 6 Aug 2021 13:24:35 +0100 Subject: [PATCH] --- openpower/sv/svp64.mdwn | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn index 34528649c..b15d58e63 100644 --- a/openpower/sv/svp64.mdwn +++ b/openpower/sv/svp64.mdwn @@ -191,7 +191,8 @@ These are the modes: * **normal** mode is straight vectorisation. no augmentations: the vector comprises an array of independently created results. * **ffirst** or data-dependent fail-on-first: see separate section. the vector may be truncated depending on certain criteria. *VL is altered as a result*. -* **sat mode** or saturation: clamps each elemrnt result to a min/max rather than overflows / wraps. allows signed and unsigned clamping. +* **sat mode** or saturation: clamps each element result to a min/max rather than overflows / wraps. allows signed and unsigned clamping for both INT +and FP. * **reduce mode**. a mapreduce is performed. the result is a scalar. a result vector however is required, as the upper elements may be used to store intermediary computations. the result of the mapreduce is in the first element with a nonzero predicate bit. see [[appendix]] note that there are comprehensive caveats when using this mode. * **pred-result** will test the result (CR testing selects a bit of CR and inverts it, just like branch testing) and if the test fails it is as if the predicate bit was zero. When Rc=1 the CR element however is still stored in the CR regfile, even if the test failed. This scheme does not apply to crops (crand, cror). See appendix for details. -- 2.30.2