From 9e012462f53113dc9ed00d7fbb89aeafeb9b89e9 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 2 Feb 2017 19:25:49 -0800
Subject: [PATCH] Fix interrupt delegation for coprocessors

---
 riscv/execute.cc   |  2 +-
 riscv/extension.cc |  7 +------
 riscv/processor.cc | 11 ++---------
 riscv/processor.h  |  5 ++---
 4 files changed, 6 insertions(+), 19 deletions(-)

diff --git a/riscv/execute.cc b/riscv/execute.cc
index eb9fe4b..ebc9dc7 100644
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -96,7 +96,7 @@ void processor_t::step(size_t n)
 
     try
     {
-      take_interrupt();
+      take_pending_interrupt();
 
       if (unlikely(slow_path()))
       {
diff --git a/riscv/extension.cc b/riscv/extension.cc
index 5321c42..a34dd80 100644
--- a/riscv/extension.cc
+++ b/riscv/extension.cc
@@ -14,12 +14,7 @@ void extension_t::illegal_instruction()
 
 void extension_t::raise_interrupt()
 {
-  reg_t prv = p->get_state()->prv;
-  reg_t mie = get_field(p->get_state()->mstatus, MSTATUS_MIE);
-
-  if (prv < PRV_M || (prv == PRV_M && mie))
-    p->raise_interrupt(IRQ_COP);
-
+  p->take_interrupt((reg_t)1 << IRQ_COP); // must not return
   throw std::logic_error("a COP exception was posted, but interrupts are disabled!");
 }
 
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 7417acf..9a6a4e2 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -154,11 +154,6 @@ void processor_t::reset()
     ext->reset(); // reset the extension
 }
 
-void processor_t::raise_interrupt(reg_t which)
-{
-  throw trap_t(((reg_t)1 << (max_xlen-1)) | which);
-}
-
 // Count number of contiguous 0 bits starting from the LSB.
 static int ctz(reg_t val)
 {
@@ -169,10 +164,8 @@ static int ctz(reg_t val)
   return res;
 }
 
-void processor_t::take_interrupt()
+void processor_t::take_interrupt(reg_t pending_interrupts)
 {
-  reg_t pending_interrupts = state.mip & state.mie;
-
   reg_t mie = get_field(state.mstatus, MSTATUS_MIE);
   reg_t m_enabled = state.prv < PRV_M || (state.prv == PRV_M && mie);
   reg_t enabled_interrupts = pending_interrupts & ~state.mideleg & -m_enabled;
@@ -182,7 +175,7 @@ void processor_t::take_interrupt()
   enabled_interrupts |= pending_interrupts & state.mideleg & -s_enabled;
 
   if (enabled_interrupts)
-    raise_interrupt(ctz(enabled_interrupts));
+    throw trap_t(((reg_t)1 << (max_xlen-1)) | ctz(enabled_interrupts));
 }
 
 void processor_t::set_privilege(reg_t prv)
diff --git a/riscv/processor.h b/riscv/processor.h
index 8a9ff47..0224f10 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -167,7 +167,6 @@ public:
   void reset();
   void step(size_t n); // run for n cycles
   void set_csr(int which, reg_t val);
-  void raise_interrupt(reg_t which);
   reg_t get_csr(int which);
   mmu_t* get_mmu() { return mmu; }
   state_t* get_state() { return &state; }
@@ -297,8 +296,8 @@ private:
   static const size_t OPCODE_CACHE_SIZE = 8191;
   insn_desc_t opcode_cache[OPCODE_CACHE_SIZE];
 
-  void check_timer();
-  void take_interrupt(); // take a trap if any interrupts are pending
+  void take_pending_interrupt() { take_interrupt(state.mip & state.mie); }
+  void take_interrupt(reg_t mask); // take first enabled interrupt in mask
   void take_trap(trap_t& t, reg_t epc); // take an exception
   void disasm(insn_t insn); // disassemble and print an instruction
   int paddr_bits();
-- 
2.30.2