From 9e0fb36f051d33efd48370967ca6bd3e005157b7 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Thu, 17 Dec 2020 14:36:43 +0000
Subject: [PATCH]

---
 openpower/sv/svp_rewrite/svp64.mdwn | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index c2cc7d20a..e89449a20 100644
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -64,7 +64,7 @@ Shows all fields in the Remapped Encoding `RM[0:23]` for all instruction variant
 * `RM-1P-3S1D` Single Predication dest/src1/2/3, applies to 4-operand instructions (fmadd, isel, madd).
 * `RM-1P-2S1D` Single Predication dest/src1/2 applies to 3-operand instructions (src1 src2 dest)
 * `RM-2P-1S1D` Twin Predication (src=1, dest=1)
-* `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST
+* `RM-2P-2S1D` Twin Predication (src=2, dest=1) primarily for LDST (Indexed)
 
 ## RM-1P-3S1D
 
@@ -557,13 +557,17 @@ Instructions are broken down by Register Profiles as listed in the following aut
 [[opcode_regs_deduped]].  "Non-SV" indicates that the operations with this Register Profile cannot be Vectorised (mtspr, bc, dcbz, twi)
 
 ## LDST-1R-1W-imm
-TBD
+
+`RM-2P-2S1D`
+
 ## LDST-1R-2W-imm
 TBD
 ## LDST-2R-imm
 TBD
 ## LDST-2R-1W
-TBD
+
+`RM-2P-2S1D`
+
 ## LDST-2R-1W-imm
 TBD
 ## LDST-2R-2W
-- 
2.30.2