From 9e31bf357e7c1550bf0878e6b60f0b6cb45cf3e5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 28 Feb 2020 16:33:18 +0100 Subject: [PATCH] interconnect/axi: remove Record inheritance on AXIInterface/AXILiteInterface. --- litex/soc/interconnect/axi.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py index 64d88ff3..af4196da 100644 --- a/litex/soc/interconnect/axi.py +++ b/litex/soc/interconnect/axi.py @@ -55,7 +55,7 @@ def r_description(data_width, id_width): ("id", id_width) ] -class AXIInterface(Record): +class AXIInterface: def __init__(self, data_width=32, address_width=32, id_width=1, clock_domain="sys"): self.data_width = data_width self.address_width = address_width @@ -88,7 +88,7 @@ def r_lite_description(data_width): ("data", data_width) ] -class AXILiteInterface(Record): +class AXILiteInterface: def __init__(self, data_width=32, address_width=32, clock_domain="sys"): self.data_width = data_width self.address_width = address_width -- 2.30.2