From 9e32ca895c9d43620d62c63d7f3cc99da6b5df3a Mon Sep 17 00:00:00 2001 From: Nick Clifton Date: Mon, 25 Feb 2002 10:34:25 +0000 Subject: [PATCH] Add documentation of IA64 port --- gas/ChangeLog | 5 ++ gas/doc/as.texinfo | 12 ++++ gas/doc/c-ia64.texi | 157 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 174 insertions(+) create mode 100644 gas/doc/c-ia64.texi diff --git a/gas/ChangeLog b/gas/ChangeLog index 14bc3188364..5fb24c254b0 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,8 @@ +2002-02-25 David Mosberger + + * doc/as.texinfo: Add entry for IA64. + * doc/c-ia64.texi: New file. + 2002-02-25 Alan Modra * config/tc-hppa.c: Update copyright date. diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo index 2e21a63b5bc..f4947e70997 100644 --- a/gas/doc/as.texinfo +++ b/gas/doc/as.texinfo @@ -42,6 +42,7 @@ @set I80386 @set I860 @set I960 +@set IA-64 @set M32R @set M68HC11 @set M680X0 @@ -335,6 +336,13 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. @end ifset @ifset M32R +@emph{Target IA-64 options:} + [@b{-mconstant-gp}|@b{-mauto-pic}] + [@b{-milp32}|@b{-milp64}|@b{-mlp64}|@b{-mp64}] + [@b{-mle}|@b{mbe}] + [@b{-x}|@b{-xexplicit}] [@b{-xauto}] [@b{-xdebug}] +@end ifset + @emph{Target M32R options:} [@b{--m32rx}|@b{--[no-]warn-explicit-parallel-conflicts}| @b{--W[n]p}] @@ -5769,6 +5777,10 @@ family. @include c-i960.texi @end ifset +@ifset IA64 +@include c-ia64.texi +@end ifset + @ifset M32R @include c-m32r.texi @end ifset diff --git a/gas/doc/c-ia64.texi b/gas/doc/c-ia64.texi new file mode 100644 index 00000000000..0885f1b3b99 --- /dev/null +++ b/gas/doc/c-ia64.texi @@ -0,0 +1,157 @@ +@c Copyright 2002 +@c Free Software Foundation, Inc. +@c Contributed by David Mosberger-Tang +@c This is part of the GAS manual. +@c For copying conditions, see the file as.texinfo. + +@ifset GENERIC +@page +@node IA-64-Dependent +@chapter IA-64 Dependent Features +@end ifset + +@ifclear GENERIC +@node Machine Dependencies +@chapter IA-64 Dependent Features +@end ifclear + +@cindex IA-64 support +@menu +* IA-64 Options:: Options +* IA-64 Syntax:: Syntax +@c * IA-64 Floating Point:: Floating Point // to be written +@c * IA-64 Directives:: IA-64 Machine Directives // to be written +* IA-64 Opcodes:: Opcodes +@end menu + +@node IA-64 Options +@section Options +@cindex IA-64 options +@cindex options for IA-64 + +@table @option +@cindex @code{-mconstant-gp} command line option, IA-64 + +@item -mconstant-gp +This option instructs the assembler to mark the resulting object file +as using the ``constant GP'' model. With this model, it is assumed +that the entire program uses a single global pointer (GP) value. Note +that this option does not in any fashion affect the machine code +emitted by the assembler. All it does is turn on the EF_IA_64_CONS_GP +flag in the ELF file header. + +@item -mauto-pic +This option instructs the assembler to mark the resulting object file +as using the ``constant GP without function descriptor'' data model. +This model is like the ``constant GP'' model, except that it +additionaly does away with function descriptors. What this means is +that the address of a function refers directly to the function's code +entry-point. Normally, such an address would refer to a function +descriptor, which contains both the code entry-point and the GP-value +needed by the function. Note that this option does not in any fashion +affect the machine code emitted by the assembler. All it does is +turn on the EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header. + +@item -milp32 +@item -milp64 +@item -mlp64 +@item -mp64 +These options select the data model. The assembler defaults to @code{-mlp64} +(LP64 data model). + +@item -mle +@item -mbe +These options select the byte order. The @code{-mle} option selects little-endian +byte order (default) and @code{-mbe} selects big-endian byte order. Note that +IA-64 machine code always uses little-endian byte order. + +@item -x +@item -xexplicit +These options turn on dependency violation checking. This checking is turned on by +default. + +@item -xauto +This option instructs the assembler to automatically insert stop bits where necessary +to remove dependency violations. + +@item -xdebug +This turns on debug output intended to help tracking down bugs in the dependency +violation checker. + +@end table + +@cindex IA-64 Syntax +@node IA-64 Syntax +@section Syntax +The assembler syntax closely follows the IA-64 Assembly Language +Reference Guide. + +@menu +* IA-64-Chars:: Special Characters +* IA-64-Regs:: Register Names +* IA-64-Bits:: Bit Names +* IA-64-Relocs:: Relocations +@end menu + +@node IA-64-Chars +@subsection Special Characters + +@cindex line comment character, IA-64 +@cindex IA-64 line comment character +@samp{//} is the line comment token. + +@cindex line separator, IA-64 +@cindex statement separator, IA-64 +@cindex IA-64 line separator +@samp{;} can be used instead of a newline to separate statements. + +@node IA-64-Regs +@subsection Register Names +@cindex IA-64 registers +@cindex register names, IA-64 + +The 128 integer registers are refered to as @samp{r@var{n}}. +The 128 floating-point registers are refered to as @samp{f@var{n}}. +The 128 application registers are refered to as @samp{ar@var{n}}. +The 128 control registers are refered to as @samp{cr@var{n}}. +The 64 one-bit predicate registers are refered to as @samp{p@var{n}}. +The 8 branch registers are refered to as @samp{b@var{n}}. +In addition, the assembler defines a number of aliases: +@samp{gp} (@samp{r1}), @samp{sp} (@samp{r12}), @samp{rp} (@samp{b0}), +@samp{ret0} (@samp{r8}), @samp{ret1} (@samp{r9}), @samp{ret2} (@samp{r10}), +@samp{ret3} (@samp{r9}), @samp{farg@var{n}} (@samp{f8+@var{n}}), and +@samp{fret@var{n}} (@samp{f8+@var{n}}). + +For convenience, the assembler also defines aliases for all named application +and control registers. For example, @samp{ar.bsp} refers to the register +backing store pointer (@samp{ar17}). Similarly, @samp{cr.eoi} refers to +the end-of-interrupt register (@samp{cr67}). + +@node IA-64-Bits +@subsection IA-64 Processor-Status-Register (PSR) Bit Names +@cindex IA-64 Processor-status-Register bit names +@cindex PSR bits +@cindex bit names, IA-64 + +The assembler defines bit masks for each of the bits in the IA-64 +processor status register. For example, @samp{psr.ic} corresponds to +a value of 0x2000. These masks are primarily intended for use with +the @sample{ssm}/@sample{sum} and @sample{rsm}/@sample{rum} +instructions, but they can be used anywhere else where an integer +constant is expected. + +@node IA-64 Opcodes +@section Opcodes +For detailed information on the IA-64 machine instruction set, see the +@c Attempt to work around a very overfull hbox. +@iftex +IA-64 Assembly Language Reference Guide available at +@smallfonts +@example +http://developer.intel.com/design/itanium/arch_spec.htm +@end example +@textfonts +@end iftex +@ifnottex +@uref{http://developer.intel.com/design/itanium/arch_spec.htm,IA-64 Architecture Handbook}. +@end ifnottex -- 2.30.2