From 9e537a76b5a0487e0788054091132d2fd7f1a0dd Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 12:20:18 -0700
Subject: [PATCH] Move $dffe to dffs.{v,ys}

---
 tests/ice40/adffs.v  | 10 ----------
 tests/ice40/adffs.ys |  9 ++++++---
 tests/ice40/dffs.v   | 34 +++++++++++++++++++++++++++++++++-
 tests/ice40/dffs.ys  |  6 ++----
 4 files changed, 41 insertions(+), 18 deletions(-)

diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v
index af7022c79..972184cfa 100644
--- a/tests/ice40/adffs.v
+++ b/tests/ice40/adffs.v
@@ -22,16 +22,6 @@ module adffn
             q <= d;
 endmodule
 
-module dffe
-    ( input d, clk, en, output reg q );
-    initial begin
-      q = 0;
-    end
-	always @( posedge clk )
-		if ( en )
-			q <= d;
-endmodule
-
 module dffsr
     ( input d, clk, pre, clr, output reg q );
     initial begin
diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys
index aee8cd6b4..d58ce1a82 100644
--- a/tests/ice40/adffs.ys
+++ b/tests/ice40/adffs.ys
@@ -1,8 +1,11 @@
 read_verilog adffs.v
 proc
-dff2dffe
-synth_ice40
-select -assert-count 2 t:SB_DFFR
+async2sync
+synth -flatten -run coarse # technology-independent coarse grained synthesis
+equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:SB_DFF
 select -assert-count 1 t:SB_DFFE
 select -assert-count 4 t:SB_LUT4
 #select -assert-none t:SB_LUT4 t:SB_DFFR t:SB_DFFE t:$_DFFSR_NPP_ t:$_DFFSR_PPP_ %% t:* %D
diff --git a/tests/ice40/dffs.v b/tests/ice40/dffs.v
index d57c8c97c..d97840c43 100644
--- a/tests/ice40/dffs.v
+++ b/tests/ice40/dffs.v
@@ -1,5 +1,37 @@
-module top
+module dff
     ( input d, clk, output reg q );
 	always @( posedge clk )
             q <= d;
 endmodule
+
+module dffe
+    ( input d, clk, en, output reg q );
+    initial begin
+      q = 0;
+    end
+	always @( posedge clk )
+		if ( en )
+			q <= d;
+endmodule
+
+module top (
+input clk,
+input en,
+input a,
+output b,b1,
+);
+
+dff u_dff (
+        .clk (clk ),
+        .d (a ),
+        .q (b )
+    );
+
+dffe u_ndffe (
+        .clk (clk ),
+        .en (en),
+        .d (a ),
+        .q (b1 )
+    );
+
+endmodule
diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys
index 0fa0bc3eb..ddd8e5734 100644
--- a/tests/ice40/dffs.ys
+++ b/tests/ice40/dffs.ys
@@ -1,11 +1,9 @@
 read_verilog dffs.v
-proc
-flatten
-dff2dffe
 hierarchy -top top
 synth -flatten -run coarse # technology-independent coarse grained synthesis
 equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check same as technology-dependent fine-grained synthesis
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 select -assert-count 1 t:SB_DFF
-select -assert-none t:SB_DFF %% t:* %D
+select -assert-count 1 t:SB_DFFE
+select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D
-- 
2.30.2