From 9e5419f57daf3cdd381d004c1a5e42a9ecda1c05 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Fri, 2 Aug 2019 01:50:22 +0100 Subject: [PATCH] update to nmutil Memory API --- src/nmutil/queue.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/nmutil/queue.py b/src/nmutil/queue.py index 9407e5e0..069aa22c 100644 --- a/src/nmutil/queue.py +++ b/src/nmutil/queue.py @@ -62,7 +62,7 @@ class Queue(FIFOInterface, Elaboratable): # set up an SRAM. XXX bug in Memory: cannot create SRAM of depth 1 ram = Memory(self.width, self.depth if self.depth > 1 else 2) - m.submodules.ram_read = ram_read = ram.read_port(synchronous=False) + m.submodules.ram_read = ram_read = ram.read_port(domain="comb") m.submodules.ram_write = ram_write = ram.write_port() # convenience names, for people familiar with ready/valid terminology -- 2.30.2