From 9e8175fc759478a7a496ac0d492cb4b6d0f13799 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 08:42:29 +0200
Subject: [PATCH] Check flops one by one

---
 tests/ecp5/adffs.v  | 40 ----------------------------------------
 tests/ecp5/adffs.ys | 41 ++++++++++++++++++++++++++++++++++++-----
 tests/ecp5/dffs.v   | 22 ----------------------
 tests/ecp5/dffs.ys  | 18 ++++++++++++++----
 4 files changed, 50 insertions(+), 71 deletions(-)

diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v
index 05e68caf7..223b52d21 100644
--- a/tests/ecp5/adffs.v
+++ b/tests/ecp5/adffs.v
@@ -45,43 +45,3 @@ module ndffnr
 		else
             q <= d;
 endmodule
-
-module top (
-input clk,
-input clr,
-input pre,
-input a,
-output b,b1,b2,b3
-);
-
-dffs u_dffs (
-        .clk (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b )
-    );
-
-ndffnr u_ndffnr (
-        .clk (clk ),
-        .clr (clr),
-        .pre (pre),
-        .d (a ),
-        .q (b1 )
-    );
-
-adff u_adff (
-        .clk (clk ),
-        .clr (clr),
-        .d (a ),
-        .q (b2 )
-    );
-
-adffn u_adffn (
-        .clk (clk ),
-        .clr (clr),
-        .d (a ),
-        .q (b3 )
-    );
-
-endmodule
diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys
index fc1363a32..658f302d0 100644
--- a/tests/ecp5/adffs.ys
+++ b/tests/ecp5/adffs.ys
@@ -1,9 +1,40 @@
 read_verilog adffs.v
+design -save read
+
 proc
-flatten
-equiv_opt -multiclock -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+hierarchy -top adff
+equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 4 t:TRELLIS_FF
-select -assert-count 3 t:LUT4
+cd adff # Constrain all select calls below inside the top module
+select -assert-count 1 t:TRELLIS_FF
+select -assert-none t:TRELLIS_FF %% t:* %D
+
+design -load read
+proc
+hierarchy -top adffn
+equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd adffn # Constrain all select calls below inside the top module
+select -assert-count 1 t:TRELLIS_FF
+select -assert-count 1 t:LUT4
+select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
+
+design -load read
+proc
+hierarchy -top dffs
+equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffs # Constrain all select calls below inside the top module
+select -assert-count 1 t:TRELLIS_FF
+select -assert-count 1 t:LUT4
+select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
+
+design -load read
+proc
+hierarchy -top ndffnr
+equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd ndffnr # Constrain all select calls below inside the top module
+select -assert-count 1 t:TRELLIS_FF
+select -assert-count 1 t:LUT4
 select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D
diff --git a/tests/ecp5/dffs.v b/tests/ecp5/dffs.v
index d97840c43..3418787c9 100644
--- a/tests/ecp5/dffs.v
+++ b/tests/ecp5/dffs.v
@@ -13,25 +13,3 @@ module dffe
 		if ( en )
 			q <= d;
 endmodule
-
-module top (
-input clk,
-input en,
-input a,
-output b,b1,
-);
-
-dff u_dff (
-        .clk (clk ),
-        .d (a ),
-        .q (b )
-    );
-
-dffe u_ndffe (
-        .clk (clk ),
-        .en (en),
-        .d (a ),
-        .q (b1 )
-    );
-
-endmodule
diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys
index 5510bb440..93b8595ad 100644
--- a/tests/ecp5/dffs.ys
+++ b/tests/ecp5/dffs.ys
@@ -1,9 +1,19 @@
 read_verilog dffs.v
-hierarchy -top top
+design -save read
+
 proc
-flatten
+hierarchy -top dff
 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
-select -assert-count 2 t:TRELLIS_FF
+cd dff # Constrain all select calls below inside the top module
+select -assert-count 1 t:TRELLIS_FF
 select -assert-none t:TRELLIS_FF %% t:* %D
+
+design -load read
+proc
+hierarchy -top dffe
+equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd dffe # Constrain all select calls below inside the top module
+select -assert-count 1 t:TRELLIS_FF
+select -assert-none t:TRELLIS_FF %% t:* %D
\ No newline at end of file
-- 
2.30.2