From 9e94f41b89bca54f8a3ce2e8e54c0467a7e8c43d Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 22 Jul 2014 23:49:26 +0200 Subject: [PATCH] SigSpec refactoring: Added RTLIL::SigSpecIterator --- kernel/rtlil.h | 34 ++++++++++++++++++++++++++++------ 1 file changed, 28 insertions(+), 6 deletions(-) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index da3a2661e..53770088b 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -69,6 +69,7 @@ namespace RTLIL struct Cell; struct SigChunk; struct SigBit; + struct SigSpecIterator; struct SigSpec; struct CaseRule; struct SwitchRule; @@ -494,6 +495,14 @@ struct RTLIL::SigBit { } }; +struct RTLIL::SigSpecIterator { + RTLIL::SigSpec *sig_p; + int index; + inline RTLIL::SigBit &operator*() const; + inline bool operator!=(const RTLIL::SigSpecIterator &other) { return index != other.index; } + inline void operator++() { index++; } +}; + struct RTLIL::SigSpec { private: std::vector chunks_; // LSB at index 0 @@ -504,6 +513,11 @@ private: void unpack() const; bool packed() const; + inline void inline_unpack() const { + if (!chunks_.empty()) + unpack(); + } + public: SigSpec(); SigSpec(const RTLIL::Const &data); @@ -513,17 +527,21 @@ public: SigSpec(int val, int width = 32); SigSpec(RTLIL::State bit, int width = 1); SigSpec(RTLIL::SigBit bit, int width = 1); + SigSpec(std::vector chunks); SigSpec(std::vector bits); SigSpec(std::set bits); - std::vector &chunks_rw() { pack(); return chunks_; } - const std::vector &chunks() const { pack(); return chunks_; } - const std::vector &bits() const { unpack(); return bits_; } + inline std::vector &chunks_rw() { pack(); return chunks_; } + inline const std::vector &chunks() const { pack(); return chunks_; } + inline const std::vector &bits() const { inline_unpack(); return bits_; } - int size() const { return width_; } + inline int size() const { return width_; } - RTLIL::SigBit &operator[](int index) { unpack(); return bits_.at(index); } - const RTLIL::SigBit &operator[](int index) const { unpack(); return bits_.at(index); } + inline RTLIL::SigBit &operator[](int index) { inline_unpack(); return bits_.at(index); } + inline const RTLIL::SigBit &operator[](int index) const { inline_unpack(); return bits_.at(index); } + + inline RTLIL::SigSpecIterator begin() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = 0; return it; } + inline RTLIL::SigSpecIterator end() { RTLIL::SigSpecIterator it; it.sig_p = this; it.index = width_; return it; } void expand(); void optimize(); @@ -582,6 +600,10 @@ public: void check() const; }; +inline RTLIL::SigBit &RTLIL::SigSpecIterator::operator*() const { + return (*sig_p)[index]; +} + inline RTLIL::SigBit::SigBit(const RTLIL::SigSpec &sig) { assert(sig.size() == 1 && sig.chunks().size() == 1); *this = SigBit(sig.chunks()[0]); -- 2.30.2