From 9ea3f78e48c89d2bb6c8554b5ea3226b92c55e1c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 28 Oct 2018 06:23:29 +0000 Subject: [PATCH] add link --- simple_v_extension/specification.mdwn | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/simple_v_extension/specification.mdwn b/simple_v_extension/specification.mdwn index 64a666194..328f73164 100644 --- a/simple_v_extension/specification.mdwn +++ b/simple_v_extension/specification.mdwn @@ -1386,7 +1386,7 @@ This example illustrates that considerable care therefore needs to be taken to ensure that left and right shift operations are implemented correctly. -## Polymorphic elwidth on LOAD/STORE +## Polymorphic elwidth on LOAD/STORE Polymorphic element widths in vectorised form means that the data being loaded (or stored) across multiple registers needs to be treated @@ -1493,7 +1493,8 @@ as follows: Note when comparing against for example the twin-predicated c.mv pseudo-code, the pattern of independent incrementing of rd and rs -is preserved unchanged. +is preserved unchanged. Note also that, just as with the c.mv +pseudocode, zeroing is not included and must be taken into account. ## Why SV bitwidth specification is restricted to 4 entries -- 2.30.2