From 9eaae9af1234fc3adaf35a1548b14d7553c82e26 Mon Sep 17 00:00:00 2001
From: lkcl <lkcl@web>
Date: Fri, 16 Oct 2020 17:18:12 +0100
Subject: [PATCH]

---
 openpower/openpower/sv/predication.mdwn | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/openpower/openpower/sv/predication.mdwn b/openpower/openpower/sv/predication.mdwn
index 5b026cf54..f548a9020 100644
--- a/openpower/openpower/sv/predication.mdwn
+++ b/openpower/openpower/sv/predication.mdwn
@@ -1,5 +1,7 @@
 # TODO
 
+<https://bugs.libre-soc.org/show_bug.cgi?id=213>
+
 * idea 1: modify cmp (and other CR generators?) with qualifiers that create single bit prefix vector into int reg
 * idea 2: override CR SO field in vector form to be predicate bit per element
 * idea 3: reading of predicates is from bits of int reg
-- 
2.30.2