From 9eace8f36032665394e582a60fc58be0a7c9303b Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 16 Apr 2020 12:48:40 -0700
Subject: [PATCH] design: add test

---
 tests/various/design.ys  | 18 +++++++++++++-----
 tests/various/design1.ys |  9 +++++++++
 2 files changed, 22 insertions(+), 5 deletions(-)
 create mode 100644 tests/various/design1.ys

diff --git a/tests/various/design.ys b/tests/various/design.ys
index f13ad8171..a64430dc7 100644
--- a/tests/various/design.ys
+++ b/tests/various/design.ys
@@ -1,9 +1,17 @@
 read_verilog <<EOT
+(* blackbox *)
+module bb(input i, output o);
+endmodule
+
+(* whitebox *)
+module wb(input i, output o);
+assign o = ~i;
+endmodule
+
 module top(input i, output o);
-assign o = i;
+assign o = ~i;
 endmodule
 EOT
-design -stash foo
-design -delete foo
-logger -expect error "No saved design 'foo' found!" 1
-design -delete foo
+
+design -stash gate
+design -import gate -as gate
diff --git a/tests/various/design1.ys b/tests/various/design1.ys
new file mode 100644
index 000000000..f13ad8171
--- /dev/null
+++ b/tests/various/design1.ys
@@ -0,0 +1,9 @@
+read_verilog <<EOT
+module top(input i, output o);
+assign o = i;
+endmodule
+EOT
+design -stash foo
+design -delete foo
+logger -expect error "No saved design 'foo' found!" 1
+design -delete foo
-- 
2.30.2