From 9eb1beea041498af7bf99ed2142d72283ce1fd48 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 12 Jan 2018 13:54:10 +1100 Subject: [PATCH] fix DDR3 on arty --- litex/boards/targets/arty.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index bec4f81a..c3e5dd70 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -108,6 +108,8 @@ class BaseSoC(SoCSDRAM): # sdram self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram")) + self.add_constant("READ_LEVELING_BITSLIP", 3) + self.add_constant("READ_LEVELING_DELAY", 14) sdram_module = MT41K128M16(self.clk_freq, "1:4") self.register_sdram(self.ddrphy, sdram_module.geom_settings, -- 2.30.2