From 9eb3039d3fb8c65b79e8a81ed83b6e0fe23e9a3c Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 12:53:41 +0100 Subject: [PATCH] missing a fastregs write-port --- src/soc/regfile/regfiles.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py index 895739a1..5ba3b917 100644 --- a/src/soc/regfile/regfiles.py +++ b/src/soc/regfile/regfiles.py @@ -63,7 +63,8 @@ class FastRegs(RegFileArray): def __init__(self): super().__init__(64, 8) self.w_ports = [self.write_port("dest1"), - self.write_port("dest2")] + self.write_port("dest2"), + self.write_port("dest3")] self.r_ports = [self.read_port("src1"), self.read_port("src2"), self.read_port("src3")] -- 2.30.2