From 9ec765ed8bc75a2e6ffb2a3c28f938a3222571b3 Mon Sep 17 00:00:00 2001
From: Las Safin <me@las.rs>
Date: Wed, 15 Sep 2021 19:21:19 +0000
Subject: [PATCH] Include Litex dependency

---
 flake.lock       | 25 +++++++++++++++++++++----
 flake.nix        | 10 +++++++---
 nix/c4m-jtag.nix |  1 -
 nix/ilang.nix    | 15 ++++++++-------
 nix/verilog.nix  | 18 +++++++++++++++---
 5 files changed, 51 insertions(+), 18 deletions(-)

diff --git a/flake.lock b/flake.lock
index 874e06e0..0fd76ec0 100644
--- a/flake.lock
+++ b/flake.lock
@@ -16,18 +16,34 @@
         "url": "https://git.libre-soc.org/git/c4m-jtag.git"
       }
     },
+    "nix-litex": {
+      "flake": false,
+      "locked": {
+        "lastModified": 1631733568,
+        "narHash": "sha256-2w63+QxzZS1jX9GXDhXFEIL1C9JcdJUlZ12Sg4GGiZ0=",
+        "owner": "L-as",
+        "repo": "tock-litex",
+        "rev": "46910f86e5610795efe9a9aa71a25592df429c6b",
+        "type": "github"
+      },
+      "original": {
+        "owner": "L-as",
+        "repo": "tock-litex",
+        "type": "github"
+      }
+    },
     "nixpkgs": {
       "locked": {
-        "lastModified": 1630612789,
-        "narHash": "sha256-f1q5ExkMX2CBqBcRmrlnpewADt3EjhyncP/PfwUhK/Q=",
+        "lastModified": 1631723418,
+        "narHash": "sha256-Sbey1S81fXUKcEHVCMwlXMju/IoCQxMwP1PPkVYpGrc=",
         "owner": "L-as",
         "repo": "nixpkgs",
-        "rev": "11f9ff27bc66bf653ccbbfae1412e6f5705e4a5c",
+        "rev": "8bfc1026477692b933df6eeec27bd494cac3e436",
         "type": "github"
       },
       "original": {
         "owner": "L-as",
-        "ref": "alliance",
+        "ref": "libresoc",
         "repo": "nixpkgs",
         "type": "github"
       }
@@ -67,6 +83,7 @@
     "root": {
       "inputs": {
         "c4m-jtag": "c4m-jtag",
+        "nix-litex": "nix-litex",
         "nixpkgs": "nixpkgs",
         "nmigen": "nmigen",
         "nmigen-soc": "nmigen-soc"
diff --git a/flake.nix b/flake.nix
index e53653aa..60314d1a 100644
--- a/flake.nix
+++ b/flake.nix
@@ -3,15 +3,17 @@
 {
   description = "FOSS CPU/GPU/VPU/SoC all in one, see https://libre-soc.org/";
 
-  inputs.nixpkgs.url = "github:L-as/nixpkgs?ref=alliance"; # for alliance
+  inputs.nixpkgs.url = "github:L-as/nixpkgs?ref=libresoc"; # for alliance and migen
   inputs.c4m-jtag.url = "git+https://git.libre-soc.org/git/c4m-jtag.git";
   inputs.c4m-jtag.flake = false;
   inputs.nmigen.url = "git+https://git.libre-soc.org/git/nmigen.git";
   inputs.nmigen.flake = false;
   inputs.nmigen-soc.url = "git+https://git.libre-soc.org/git/nmigen-soc.git";
   inputs.nmigen-soc.flake = false;
+  inputs.nix-litex.url = "github:L-as/tock-litex";
+  inputs.nix-litex.flake = false;
 
-  outputs = { self, nixpkgs, c4m-jtag, nmigen, nmigen-soc }:
+  outputs = { self, nixpkgs, c4m-jtag, nmigen, nmigen-soc, nix-litex }:
     let
       getv = x: builtins.substring 0 8 x.lastModifiedDate;
 
@@ -20,6 +22,8 @@
       forAllSystems = nixpkgs.lib.genAttrs supportedSystems;
 
       nixpkgsFor = forAllSystems (system: import nixpkgs { inherit system; overlays = [ self.overlay ]; });
+
+      litexPkgs = pkgs: import "${nix-litex}/pkgs" { inherit pkgs; };
     in
     {
       overlay = final: prev: {
@@ -45,7 +49,7 @@
         };
 
         libresoc-verilog = final.callPackage (import ./nix/verilog.nix { version = getv self; }) {};
-        libresoc-ilang = final.callPackage (import ./nix/ilang.nix { version = getv self; }) {};
+        libresoc-ilang = final.callPackage (import ./nix/ilang.nix { version = getv self; litexPkgs = litexPkgs final; }) {};
       };
 
       packages = forAllSystems (system: {
diff --git a/nix/c4m-jtag.nix b/nix/c4m-jtag.nix
index 2bf8407a..cf301c67 100644
--- a/nix/c4m-jtag.nix
+++ b/nix/c4m-jtag.nix
@@ -16,7 +16,6 @@ buildPythonPackage {
   prePatch = ''
     export SETUPTOOLS_SCM_PRETEND_VERSION=${version}
   '';
-    # sed -i -e 's/use_scm_version=scm_version..,//g' setup.py
 
   meta = with lib; {
     homepage = "https://pypi.org/project/libresoc-openpower-isa/";
diff --git a/nix/ilang.nix b/nix/ilang.nix
index b9df6973..c5f548f2 100644
--- a/nix/ilang.nix
+++ b/nix/ilang.nix
@@ -1,4 +1,4 @@
-{ version }:
+{ version, litexPkgs }:
 
 { stdenv, python3Packages, yosys, libresoc-verilog }:
 
@@ -11,8 +11,8 @@ stdenv.mkDerivation {
   strictDeps = true;
 
   nativeBuildInputs = (with python3Packages; [
-    c4m-jtag nmigen-soc python libresoc-ieee754fpu libresoc-openpower-isa
-  ]) ++ [ yosys ];
+    python migen
+  ]) ++ (with litexPkgs; [ litex litedram liteeth liteiclink litescope litesdcard ]);
 
   postPatch = ''
     patchShebangs --build .
@@ -23,17 +23,18 @@ stdenv.mkDerivation {
   buildPhase = ''
     runHook preBuild
     cp ${libresoc-verilog} libresoc/libresoc.v
-    stat ls180soc.py
     ./ls180soc.py --build --platform=ls180sram4k --num-srams=2 --srams4k
-    echo IKJIJIJIJI
-    #make ls1804k
     runHook postBuild
   '';
 
   installPhase = ''
     runHook preInstall
     mkdir $out
-    mv ls180.il ls180_cvt.il libresoc_cvt.il -t $out
+    mv build/ls180sram4k/gateware/ls180sram4k.v $out/ls180.v
+    mv build/ls180sram4k/gateware/mem.init $out
+    mv build/ls180sram4k/gateware/mem_1.init $out
+    mv libresoc/libresoc.v $out
+    mv libresoc/SPBlock_512W64B8W.v $out
     runHook postInstall
   '';
 
diff --git a/nix/verilog.nix b/nix/verilog.nix
index 41b092ac..4ba3727c 100644
--- a/nix/verilog.nix
+++ b/nix/verilog.nix
@@ -1,12 +1,24 @@
 { version }:
 
-{ stdenv, python3Packages, python2, yosys }:
-
+{ stdenv, python3Packages, runCommand, python2, yosys }:
+
+let
+  # If we use ../. as source, then any change to
+  # any unrelated Nix file would cause a rebuild,
+  # since the build would have access to it.
+  src = runCommand "libresoc-verilog-source" {} ''
+    mkdir $out
+    cp -r ${../src} -T $out/src
+    cp -r ${../mkpinmux.sh} -T $out/mkpinmux.sh
+    cp -r ${../pinmux} -T $out/pinmux
+    cp -r ${../Makefile} -T $out/Makefile
+  '';
+in
 stdenv.mkDerivation {
   pname = "libresoc.v";
   inherit version;
 
-  src = ../.;
+  inherit src;
 
   strictDeps = true;
 
-- 
2.30.2