From 9ec9396e85c84403acd8f01537a5f202d3aa1697 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Thu, 4 Jun 2020 14:21:42 +0100 Subject: [PATCH] sync onto fu.go_wr_i otherwise a loop occurs --- src/soc/simple/core.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py index a6fc30ce..95aed902 100644 --- a/src/soc/simple/core.py +++ b/src/soc/simple/core.py @@ -50,7 +50,7 @@ class NonProductionCore(Elaboratable): def elaborate(self, platform): m = Module() - comb = m.d.comb + comb, sync = m.d.comb, m.d.sync m.submodules.pdecode2 = dec2 = self.pdecode2 m.submodules.fus = self.fus @@ -179,7 +179,7 @@ class NonProductionCore(Elaboratable): fu_active = fu_bitdict[funame] pick = fu.wr.rel[idx] & fu_active & wrflag comb += wrpick.i[pi].eq(pick) - comb += fu.go_wr_i[idx].eq(wrpick.o[pi]) + sync += fu.go_wr_i[idx].eq(wrpick.o[pi] & wrpick.en_o) # connect regfile port to input print ("reg connect widths", regfile, regname, pi, funame, -- 2.30.2