From 9ecfd06b8498e5ac86eecf7b990053e3cb9ed903 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 11 Jul 2020 17:34:07 +0100 Subject: [PATCH] sorting out bigendian/littleendian including in qemu qemu is a pain! --- src/soc/config/endian.py | 5 ++ src/soc/decoder/isa/caller.py | 2 +- src/soc/decoder/power_decoder.py | 8 +-- src/soc/fu/alu/test/test_pipe_caller.py | 31 ++++----- src/soc/fu/branch/test/test_pipe_caller.py | 14 ++-- src/soc/fu/compunits/test/test_compunit.py | 8 ++- src/soc/fu/compunits/test/test_cr_compunit.py | 3 +- .../compunits/test/test_logical_compunit.py | 6 +- src/soc/fu/cr/test/test_pipe_caller.py | 29 ++++---- src/soc/fu/div/test/test_pipe_caller.py | 67 ++++++++++--------- src/soc/fu/logical/test/test_pipe_caller.py | 23 ++++--- src/soc/fu/mul/test/test_pipe_caller.py | 31 ++++----- src/soc/fu/shift_rot/test/test_pipe_caller.py | 25 +++---- src/soc/fu/spr/test/test_pipe_caller.py | 15 +++-- src/soc/fu/trap/test/test_pipe_caller.py | 20 +++--- src/soc/simulator/program.py | 2 +- src/soc/simulator/qemu.py | 27 ++++++-- src/soc/simulator/test_helloworld_sim.py | 5 +- src/soc/simulator/test_mul_sim.py | 5 +- src/soc/simulator/test_sim.py | 39 +++++------ 20 files changed, 203 insertions(+), 162 deletions(-) create mode 100644 src/soc/config/endian.py diff --git a/src/soc/config/endian.py b/src/soc/config/endian.py new file mode 100644 index 00000000..eb6e0c3f --- /dev/null +++ b/src/soc/config/endian.py @@ -0,0 +1,5 @@ +global bigendian +bigendian = 0 + +def set_endian_mode(mode): + bigendian = mode diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 3c3dcce5..aeeaa5d5 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -250,7 +250,7 @@ class ISACaller: initial_insns=None, respect_pc=False, disassembly=None, initial_pc=0, - bigendian=True): + bigendian=False): self.bigendian = bigendian self.halted = False diff --git a/src/soc/decoder/power_decoder.py b/src/soc/decoder/power_decoder.py index b7d1bc15..09cdd412 100644 --- a/src/soc/decoder/power_decoder.py +++ b/src/soc/decoder/power_decoder.py @@ -343,13 +343,13 @@ class TopPowerDecoder(PowerDecoder): def elaborate(self, platform): m = PowerDecoder.elaborate(self, platform) comb = m.d.comb - # raw opcode in, byte-reverse it - raw_be = self.raw_opcode_in + # raw opcode in assumed to be in LE order: byte-reverse it to get BE + raw_le = self.raw_opcode_in l = [] for i in range(0, self.width, 8): - l.append(raw_be[i:i+8]) + l.append(raw_le[i:i+8]) l.reverse() - raw_le = Cat(*l) + raw_be = Cat(*l) comb += self.opcode_in.eq(Mux(self.bigendian, raw_be, raw_le)) # add all signal from commonly-used fields diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py index c5d250dd..6b3ae3f3 100644 --- a/src/soc/fu/alu/test/test_pipe_caller.py +++ b/src/soc/fu/alu/test/test_pipe_caller.py @@ -10,7 +10,7 @@ from soc.decoder.power_enums import (XER_bits, Function, InternalOp, CryIn) from soc.decoder.selectable_int import SelectableInt from soc.simulator.program import Program from soc.decoder.isa.all import ISA - +from soc.config.endian import bigendian from soc.fu.test.common import (TestCase, ALUHelpers) from soc.fu.alu.pipeline import ALUBasePipe @@ -81,31 +81,31 @@ class ALUTestCase(FHDLTestCase): lst = [f"extsw 3, 1"] initial_regs = [0] * 32 initial_regs[1] = 0xb6a1fc6c8576af91 - self.run_tst_program(Program(lst), initial_regs) + self.run_tst_program(Program(lst, bigendian), initial_regs) lst = [f"subf 3, 1, 2"] initial_regs = [0] * 32 initial_regs[1] = 0x3d7f3f7ca24bac7b initial_regs[2] = 0xf6b2ac5e13ee15c2 - self.run_tst_program(Program(lst), initial_regs) + self.run_tst_program(Program(lst, bigendian), initial_regs) lst = [f"subf 3, 1, 2"] initial_regs = [0] * 32 initial_regs[1] = 0x833652d96c7c0058 initial_regs[2] = 0x1c27ecff8a086c1a - self.run_tst_program(Program(lst), initial_regs) + self.run_tst_program(Program(lst, bigendian), initial_regs) lst = [f"extsb 3, 1"] initial_regs = [0] * 32 initial_regs[1] = 0x7f9497aaff900ea0 - self.run_tst_program(Program(lst), initial_regs) + self.run_tst_program(Program(lst, bigendian), initial_regs) lst = [f"add. 3, 1, 2"] initial_regs = [0] * 32 initial_regs[1] = 0xc523e996a8ff6215 initial_regs[2] = 0xe1e5b9cc9864c4a8 - self.run_tst_program(Program(lst), initial_regs) + self.run_tst_program(Program(lst, bigendian), initial_regs) lst = [f"add 3, 1, 2"] initial_regs = [0] * 32 initial_regs[1] = 0x2e08ae202742baf8 initial_regs[2] = 0x86c43ece9efe5baa - self.run_tst_program(Program(lst), initial_regs) + self.run_tst_program(Program(lst, bigendian), initial_regs) def test_rand(self): insns = ["add", "add.", "subf"] @@ -115,7 +115,7 @@ class ALUTestCase(FHDLTestCase): initial_regs = [0] * 32 initial_regs[1] = random.randint(0, (1<<64)-1) initial_regs[2] = random.randint(0, (1<<64)-1) - self.run_tst_program(Program(lst), initial_regs) + self.run_tst_program(Program(lst, bigendian), initial_regs) def test_rand_imm(self): insns = ["addi", "addis", "subfic"] @@ -126,7 +126,7 @@ class ALUTestCase(FHDLTestCase): print(lst) initial_regs = [0] * 32 initial_regs[1] = random.randint(0, (1<<64)-1) - self.run_tst_program(Program(lst), initial_regs) + self.run_tst_program(Program(lst, bigendian), initial_regs) def test_0_adde(self): lst = ["adde. 5, 6, 7"] @@ -138,7 +138,7 @@ class ALUTestCase(FHDLTestCase): xer = SelectableInt(0, 64) xer[XER_bits['CA']] = 1 initial_sprs[special_sprs['XER']] = xer - self.run_tst_program(Program(lst), initial_regs, initial_sprs) + self.run_tst_program(Program(lst, bigendian), initial_regs, initial_sprs) def test_cmp(self): lst = ["subf. 1, 6, 7", @@ -146,7 +146,7 @@ class ALUTestCase(FHDLTestCase): initial_regs = [0] * 32 initial_regs[6] = 0x10 initial_regs[7] = 0x05 - self.run_tst_program(Program(lst), initial_regs, {}) + self.run_tst_program(Program(lst, bigendian), initial_regs, {}) def test_extsb(self): insns = ["extsb", "extsh", "extsw"] @@ -156,7 +156,7 @@ class ALUTestCase(FHDLTestCase): print(lst) initial_regs = [0] * 32 initial_regs[1] = random.randint(0, (1<<64)-1) - self.run_tst_program(Program(lst), initial_regs) + self.run_tst_program(Program(lst, bigendian), initial_regs) def test_cmpeqb(self): lst = ["cmpeqb cr1, 1, 2"] @@ -164,7 +164,7 @@ class ALUTestCase(FHDLTestCase): initial_regs = [0] * 32 initial_regs[1] = i initial_regs[2] = 0x0001030507090b0f - self.run_tst_program(Program(lst), initial_regs, {}) + self.run_tst_program(Program(lst, bigendian), initial_regs, {}) def test_ilang(self): pspec = ALUPipeSpec(id_wid=2) @@ -204,7 +204,8 @@ class TestRunner(FHDLTestCase): program = test.program self.subTest(test.name) sim = ISA(pdecode2, test.regs, test.sprs, test.cr, - test.mem, test.msr) + test.mem, test.msr, + bigendian=bigendian) gen = program.generate_instructions() instructions = list(zip(gen, program.assembly.splitlines())) @@ -221,7 +222,7 @@ class TestRunner(FHDLTestCase): print ("before: so/ov/32", so, ov, ov32) # ask the decoder to decode this binary data (endian'd) - yield pdecode2.dec.bigendian.eq(0) # little / big? + yield pdecode2.dec.bigendian.eq(bigendian) # little / big? yield instruction.eq(ins) # raw binary instr. yield Settle() fn_unit = yield pdecode2.e.do.fn_unit diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py index f9582323..947cff28 100644 --- a/src/soc/fu/branch/test/test_pipe_caller.py +++ b/src/soc/fu/branch/test/test_pipe_caller.py @@ -11,6 +11,7 @@ from soc.decoder.selectable_int import SelectableInt from soc.simulator.program import Program from soc.decoder.isa.all import ISA from soc.regfile.regfiles import FastRegs +from soc.config.endian import bigendian from soc.fu.test.common import TestCase, ALUHelpers from soc.fu.branch.pipeline import BranchBasePipe @@ -83,7 +84,7 @@ class BranchTestCase(FHDLTestCase): imm = random.randrange(-1<<23, (1<<23)-1) * 4 lst = [f"{choice} {imm}"] initial_regs = [0] * 32 - self.run_tst_program(Program(lst), initial_regs) + self.run_tst_program(Program(lst, bigendian), initial_regs) def test_bc_cr(self): for i in range(20): @@ -93,7 +94,7 @@ class BranchTestCase(FHDLTestCase): cr = random.randrange(0, (1<<32)-1) lst = [f"bc {bo}, {bi}, {bc}"] initial_regs = [0] * 32 - self.run_tst_program(Program(lst), initial_cr=cr) + self.run_tst_program(Program(lst, bigendian), initial_cr=cr) def test_bc_ctr(self): for i in range(20): @@ -104,7 +105,7 @@ class BranchTestCase(FHDLTestCase): ctr = random.randint(0, (1<<32)-1) lst = [f"bc {bo}, {bi}, {bc}"] initial_sprs={9: SelectableInt(ctr, 64)} - self.run_tst_program(Program(lst), + self.run_tst_program(Program(lst, bigendian), initial_sprs=initial_sprs, initial_cr=cr) @@ -124,7 +125,7 @@ class BranchTestCase(FHDLTestCase): initial_sprs={9: SelectableInt(ctr, 64), 8: SelectableInt(lr, 64), 815: SelectableInt(tar, 64)} - self.run_tst_program(Program(lst), + self.run_tst_program(Program(lst, bigendian), initial_sprs=initial_sprs, initial_cr=cr) @@ -166,7 +167,8 @@ class TestRunner(FHDLTestCase): program = test.program self.subTest(test.name) simulator = ISA(pdecode2, test.regs, test.sprs, test.cr, - test.mem, test.msr) + test.mem, test.msr, + bigendian=bigendian) initial_cia = 0x2000 simulator.set_pc(initial_cia) gen = program.generate_instructions() @@ -181,7 +183,7 @@ class TestRunner(FHDLTestCase): print(code) # ask the decoder to decode this binary data (endian'd) - yield pdecode2.dec.bigendian.eq(0) # little / big? + yield pdecode2.dec.bigendian.eq(bigendian) # little / big? yield instruction.eq(ins) # raw binary instr. # note, here, the op will need further decoding in order # to set the correct SPRs on SPR1/2/3. op_bc* require diff --git a/src/soc/fu/compunits/test/test_compunit.py b/src/soc/fu/compunits/test/test_compunit.py index cffa0316..7a73cb83 100644 --- a/src/soc/fu/compunits/test/test_compunit.py +++ b/src/soc/fu/compunits/test/test_compunit.py @@ -11,6 +11,7 @@ from soc.decoder.isa.all import ISA from soc.experiment.compalu_multi import find_ok # hack from soc.config.test.test_loadstore import TestMemPspec + def set_cu_input(cu, idx, data): rdop = cu.get_in_name(idx) yield cu.src_i[idx].eq(data) @@ -147,12 +148,13 @@ def check_sim_memory(dut, l0, sim, code): expected_mem, actual_mem)) class TestRunner(FHDLTestCase): - def __init__(self, test_data, fukls, iodef, funit): + def __init__(self, test_data, fukls, iodef, funit, bigendian): super().__init__("run_all") self.test_data = test_data self.fukls = fukls self.iodef = iodef self.funit = funit + self.bigendian = bigendian def run_all(self): m = Module() @@ -202,7 +204,7 @@ class TestRunner(FHDLTestCase): test.msr, initial_insns=gen, respect_pc=False, disassembly=insncode, - bigendian=False) + bigendian=self.bigendian) # initialise memory if self.funit == Function.LDST: @@ -219,7 +221,7 @@ class TestRunner(FHDLTestCase): print(index, code) # ask the decoder to decode this binary data (endian'd) - yield pdecode2.dec.bigendian.eq(0) # little / big? + yield pdecode2.dec.bigendian.eq(self.bigendian) # le / be? yield instruction.eq(ins) # raw binary instr. yield Settle() fn_unit = yield pdecode2.e.do.fn_unit diff --git a/src/soc/fu/compunits/test/test_cr_compunit.py b/src/soc/fu/compunits/test/test_cr_compunit.py index 9d05d3f7..50e9d133 100644 --- a/src/soc/fu/compunits/test/test_cr_compunit.py +++ b/src/soc/fu/compunits/test/test_cr_compunit.py @@ -7,12 +7,13 @@ from soc.fu.cr.test.test_pipe_caller import CRTestCase from soc.fu.compunits.compunits import CRFunctionUnit from soc.fu.compunits.test.test_compunit import TestRunner +from soc.config.endian import bigendian class CRTestRunner(TestRunner): def __init__(self, test_data): super().__init__(test_data, CRFunctionUnit, self, - Function.CR) + Function.CR, bigendian) def get_cu_inputs(self, dec2, sim): """naming (res) must conform to CRFunctionUnit input regspec diff --git a/src/soc/fu/compunits/test/test_logical_compunit.py b/src/soc/fu/compunits/test/test_logical_compunit.py index 439901a5..877f14c5 100644 --- a/src/soc/fu/compunits/test/test_logical_compunit.py +++ b/src/soc/fu/compunits/test/test_logical_compunit.py @@ -1,17 +1,19 @@ import unittest from soc.decoder.power_enums import (XER_bits, Function) -from soc.fu.logical.test.test_pipe_caller import LogicalTestCase, get_cu_inputs +from soc.fu.logical.test.test_pipe_caller import (LogicalTestCase, + get_cu_inputs) from soc.fu.compunits.compunits import LogicalFunctionUnit from soc.fu.compunits.test.test_compunit import TestRunner from soc.fu.test.common import ALUHelpers +from soc.config.endian import bigendian class LogicalTestRunner(TestRunner): def __init__(self, test_data): super().__init__(test_data, LogicalFunctionUnit, self, - Function.LOGICAL) + Function.LOGICAL, bigendian) def get_cu_inputs(self, dec2, sim): """naming (res) must conform to LogicalFunctionUnit input regspec diff --git a/src/soc/fu/cr/test/test_pipe_caller.py b/src/soc/fu/cr/test/test_pipe_caller.py index e6e38bca..27ea17b7 100644 --- a/src/soc/fu/cr/test/test_pipe_caller.py +++ b/src/soc/fu/cr/test/test_pipe_caller.py @@ -10,7 +10,7 @@ from soc.decoder.power_enums import (XER_bits, Function) from soc.decoder.selectable_int import SelectableInt from soc.simulator.program import Program from soc.decoder.isa.all import ISA - +from soc.config.endian import bigendian from soc.fu.test.common import TestCase, ALUHelpers from soc.fu.cr.pipeline import CRBasePipe @@ -60,13 +60,13 @@ class CRTestCase(FHDLTestCase): bt = random.randint(0, 31) lst = [f"{choice} {ba}, {bb}, {bt}"] cr = random.randint(0, (1<<32)-1) - self.run_tst_program(Program(lst), initial_cr=cr) + self.run_tst_program(Program(lst, bigendian), initial_cr=cr) def test_crand(self): for i in range(20): lst = ["crand 0, 11, 13"] cr = random.randint(0, (1<<32)-1) - self.run_tst_program(Program(lst), initial_cr=cr) + self.run_tst_program(Program(lst, bigendian), initial_cr=cr) def test_1_mcrf(self): for i in range(20): @@ -74,13 +74,13 @@ class CRTestCase(FHDLTestCase): dst = random.randint(0, 7) lst = [f"mcrf {src}, {dst}"] cr = random.randint(0, (1<<32)-1) - self.run_tst_program(Program(lst), initial_cr=cr) + self.run_tst_program(Program(lst, bigendian), initial_cr=cr) def test_0_mcrf(self): for i in range(8): lst = [f"mcrf 5, {i}"] cr = 0xfeff0001 - self.run_tst_program(Program(lst), initial_cr=cr) + self.run_tst_program(Program(lst, bigendian), initial_cr=cr) def test_mtcrf(self): for i in range(20): @@ -89,7 +89,7 @@ class CRTestCase(FHDLTestCase): cr = random.randint(0, (1<<32)-1) initial_regs = [0] * 32 initial_regs[2] = random.randint(0, (1<<32)-1) - self.run_tst_program(Program(lst), initial_regs=initial_regs, + self.run_tst_program(Program(lst, bigendian), initial_regs=initial_regs, initial_cr=cr) def test_mtocrf(self): for i in range(20): @@ -98,21 +98,21 @@ class CRTestCase(FHDLTestCase): cr = random.randint(0, (1<<32)-1) initial_regs = [0] * 32 initial_regs[2] = random.randint(0, (1<<32)-1) - self.run_tst_program(Program(lst), initial_regs=initial_regs, + self.run_tst_program(Program(lst, bigendian), initial_regs=initial_regs, initial_cr=cr) def test_mfcr(self): for i in range(5): lst = ["mfcr 2"] cr = random.randint(0, (1<<32)-1) - self.run_tst_program(Program(lst), initial_cr=cr) + self.run_tst_program(Program(lst, bigendian), initial_cr=cr) def test_mfocrf(self): for i in range(20): mask = 1<>i*8) & 0xff) + + # set breakpoint at start + q.break_address(0x20000000) q.gdb_continue() + # set the MSR bit 63, to set bigendian/littleendian mode + msr = q.get_msr() + print ("msr", bigendian, hex(msr)) + if bigendian: + msr &= ~(1<<0) + else: + msr |= (1<<0) + q.gdb_eval('$msr=%d' % msr) + print ("msr set to", hex(msr)) # set the CR to 0, matching the simulator q.gdb_eval('$cr=0') # delete the previous breakpoint so loops don't screw things up @@ -134,11 +147,13 @@ def run_program(program, initial_mem=None, extra_break_addr=None): if extra_break_addr: q.break_address(extra_break_addr) q.gdb_continue() + q.set_endian(False) # how qemu gets/sets data, NOT sets arch + return q if __name__ == '__main__': - q = QemuController("qemu_test/kernel.bin") + q = QemuController("simulator/qemu_test/kernel.bin", bigendian=True) q.connect() q.break_address(0x20000000) q.gdb_continue() diff --git a/src/soc/simulator/test_helloworld_sim.py b/src/soc/simulator/test_helloworld_sim.py index 8801844d..fb5ed768 100644 --- a/src/soc/simulator/test_helloworld_sim.py +++ b/src/soc/simulator/test_helloworld_sim.py @@ -14,7 +14,7 @@ from soc.simulator.qemu import run_program from soc.decoder.isa.all import ISA from soc.fu.test.common import TestCase from soc.simulator.test_sim import DecoderBase - +from soc.config.endian import bigendian class HelloTestCases(FHDLTestCase): @@ -38,7 +38,8 @@ class HelloTestCases(FHDLTestCase): "mtspr 9, 12", # mtctr r12 "bcctrl 20,0,0", # bctrl ] - self.run_tst_program(Program(lst), [1,12], extra_break_addr=0x1014) + self.run_tst_program(Program(lst, bigendian), + [1,12], extra_break_addr=0x1014) def run_tst_program(self, prog, initial_regs=None, initial_sprs=None, initial_mem=None, extra_break_addr=None): diff --git a/src/soc/simulator/test_mul_sim.py b/src/soc/simulator/test_mul_sim.py index a3db0f13..00c51a4e 100644 --- a/src/soc/simulator/test_mul_sim.py +++ b/src/soc/simulator/test_mul_sim.py @@ -14,6 +14,7 @@ from soc.simulator.qemu import run_program from soc.decoder.isa.all import ISA from soc.fu.test.common import TestCase from soc.simulator.test_sim import DecoderBase +from soc.config.endian import bigendian @@ -28,7 +29,7 @@ class MulTestCases(FHDLTestCase): lst = ["addi 1, 0, 0x5678", "addi 2, 0, 0x1234", "mullw 3, 1, 2"] - self.run_tst_program(Program(lst), [3]) + self.run_tst_program(Program(lst, bigendian), [3]) def test_mullwo(self): lst = ["addi 1, 0, 0x5678", @@ -36,7 +37,7 @@ class MulTestCases(FHDLTestCase): "addi 2, 0, 0x1234", "neg 2, 2", "mullwo 3, 1, 2"] - self.run_tst_program(Program(lst), [3]) + self.run_tst_program(Program(lst, bigendian), [3]) def run_tst_program(self, prog, initial_regs=None, initial_sprs=None, initial_mem=None): diff --git a/src/soc/simulator/test_sim.py b/src/soc/simulator/test_sim.py index 7fa0c8a8..d1e65f4f 100644 --- a/src/soc/simulator/test_sim.py +++ b/src/soc/simulator/test_sim.py @@ -13,6 +13,7 @@ from soc.simulator.program import Program from soc.simulator.qemu import run_program from soc.decoder.isa.all import ISA from soc.fu.test.common import TestCase +from soc.config.endian import bigendian class AttnTestCase(FHDLTestCase): @@ -30,7 +31,7 @@ class AttnTestCase(FHDLTestCase): "subf. 1, 6, 7", "cmp cr2, 1, 6, 7", ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1]) def run_tst_program(self, prog, initial_regs=None, initial_sprs=None, @@ -55,7 +56,7 @@ class GeneralTestCases(FHDLTestCase): "subf. 1, 6, 7", "cmp cr2, 1, 6, 7", ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1]) @unittest.skip("disable") @@ -64,7 +65,7 @@ class GeneralTestCases(FHDLTestCase): "addi 2, 0, 0x1234", "add 3, 1, 2", "and 4, 1, 2"] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3, 4]) @unittest.skip("disable") @@ -77,7 +78,7 @@ class GeneralTestCases(FHDLTestCase): initial_mem = {0x1230: (0x5432123412345678, 8), 0x1238: (0xabcdef0187654321, 8), } - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3], initial_mem) @@ -89,7 +90,7 @@ class GeneralTestCases(FHDLTestCase): "addi 4, 0, 0x40", "stw 1, 0x40(2)", "lwbrx 3, 4, 2"] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3]) @unittest.skip("disable") @@ -99,7 +100,7 @@ class GeneralTestCases(FHDLTestCase): "addi 4, 0, 0x40", "stwbrx 1, 4, 2", "lwzx 3, 4, 2"] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3]) @unittest.skip("disable") @@ -109,7 +110,7 @@ class GeneralTestCases(FHDLTestCase): "addi 4, 0, 0x40", "stw 1, 0x40(2)", "lwzx 3, 4, 2"] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3]) @unittest.skip("disable") @@ -124,7 +125,7 @@ class GeneralTestCases(FHDLTestCase): "addi 5, 0, 0x12", "stb 5, 5(2)", "ld 5, 0(2)"] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3, 4, 5]) @unittest.skip("disable") @@ -134,7 +135,7 @@ class GeneralTestCases(FHDLTestCase): "subf 3, 1, 2", "subfic 4, 1, 0x1337", "neg 5, 1"] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3, 4, 5]) @unittest.skip("disable") @@ -146,7 +147,7 @@ class GeneralTestCases(FHDLTestCase): "addc 3, 2, 1", "addi 3, 3, 1" ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1, 2, 3]) @unittest.skip("disable") @@ -154,7 +155,7 @@ class GeneralTestCases(FHDLTestCase): lst = ["addi 1, 0, 0x0FFF", "addis 1, 1, 0x0F" ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1]) @unittest.skip("broken") @@ -162,7 +163,7 @@ class GeneralTestCases(FHDLTestCase): lst = ["addi 1, 0, 3", "mulli 1, 1, 2" ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1]) @unittest.skip("disable") @@ -181,7 +182,7 @@ class GeneralTestCases(FHDLTestCase): 0x1008: (0xabcdef0187654321, 8), 0x1020: (0x1828384822324252, 8), } - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [3,4], initial_mem) @unittest.skip("disable") @@ -199,7 +200,7 @@ class GeneralTestCases(FHDLTestCase): 0x1008: (0xabcdef0187654321, 8), 0x1020: (0x1828384822324252, 8), } - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [1,2,3,4], initial_mem) def test_loop(self): @@ -217,14 +218,14 @@ class GeneralTestCases(FHDLTestCase): "cmpi 0,1,9,12", # compare 9 to value 0, store in CR2 "bc 4,0,-8" # branch if CR2 "test was != 0" ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [9], initial_mem={}) def test_30_addis(self): lst = [#"addi 0, 0, 5", "addis 12, 0, 0", ] - with Program(lst) as program: + with Program(lst, bigendian) as program: self.run_tst_program(program, [12]) def run_tst_program(self, prog, initial_regs=None, initial_sprs=None, @@ -244,7 +245,6 @@ class DecoderBase: gen = list(generator.generate_instructions()) insn_code = generator.assembly.splitlines() instructions = list(zip(gen, insn_code)) - bigendian = False pdecode = create_pdecode() m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode) @@ -261,7 +261,7 @@ class DecoderBase: sim = Simulator(m) def process(): - #yield pdecode2.dec.bigendian.eq(1) + #yield pdecode2.dec.bigendian.eq(bigendian) yield Settle() while True: @@ -287,7 +287,8 @@ class DecoderBase: simulator = self.run_tst(prog, initial_mem=initial_mem, initial_pc=0x20000000) prog.reset() - with run_program(prog, initial_mem, extra_break_addr) as q: + with run_program(prog, initial_mem, extra_break_addr, + bigendian=bigendian) as q: self.qemu_register_compare(simulator, q, reglist) self.qemu_mem_compare(simulator, q, True) print(simulator.gpr.dump()) -- 2.30.2