From 9ed736e718dfd511f0c68896d3e3dc1c78402cb6 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sun, 17 Feb 2019 14:03:29 +0000 Subject: [PATCH] test single-cycle align phase on 64-bit add --- src/add/test_add64.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/add/test_add64.py b/src/add/test_add64.py index c7977164..950897ea 100644 --- a/src/add/test_add64.py +++ b/src/add/test_add64.py @@ -85,6 +85,6 @@ def testbench(dut): #yield from check_case(dut, 1, 1, 1) if __name__ == '__main__': - dut = FPADD(width=64) + dut = FPADD(width=64, single_cycle=True) run_simulation(dut, testbench(dut), vcd_name="test_add64.vcd") -- 2.30.2