From 9ede0bfc541192f42a5d4afe8829ee99b822dd8d Mon Sep 17 00:00:00 2001 From: whitequark Date: Fri, 20 Sep 2019 16:11:01 +0000 Subject: [PATCH] vendor.lattice_{ecp5,ice40}: allow clock constraints on arbitrary signals. Fixes #88. --- nmigen/vendor/lattice_ecp5.py | 4 ++-- nmigen/vendor/lattice_ice40.py | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/nmigen/vendor/lattice_ecp5.py b/nmigen/vendor/lattice_ecp5.py index c02e370..f4e7d38 100644 --- a/nmigen/vendor/lattice_ecp5.py +++ b/nmigen/vendor/lattice_ecp5.py @@ -121,7 +121,7 @@ class LatticeECP5Platform(TemplatedPlatform): {%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %}; {% endfor %} {% for signal, frequency in platform.iter_clock_constraints() -%} - FREQUENCY PORT "{{signal.name}}" {{frequency}} HZ; + FREQUENCY NET "{{signal|hierarchy(".")}}" {{frequency}} HZ; {% endfor %} """ } @@ -203,7 +203,7 @@ class LatticeECP5Platform(TemplatedPlatform): {%- for key, value in extras.items() %} {{key}}={{value}}{% endfor %}; {% endfor %} {% for signal, frequency in platform.iter_clock_constraints() -%} - FREQUENCY PORT "{{signal.name}}" {{frequency/1000000}} MHZ; + FREQUENCY NET "{{signal|hierarchy("/")}}" {{frequency/1000000}} MHZ; {% endfor %} {{get_override("add_preferences")|default("# (add_preferences placeholder)")}} """, diff --git a/nmigen/vendor/lattice_ice40.py b/nmigen/vendor/lattice_ice40.py index e403341..e4b2a80 100644 --- a/nmigen/vendor/lattice_ice40.py +++ b/nmigen/vendor/lattice_ice40.py @@ -97,7 +97,7 @@ class LatticeICE40Platform(TemplatedPlatform): # {{autogenerated}} {% for signal, frequency in platform.iter_clock_constraints() -%} {# Clock in MHz #} - ctx.addClock("{{signal.name}}", {{frequency/1000000}}) + ctx.addClock("{{signal|hierarchy(".")}}", {{frequency/1000000}}) {% endfor%} """, } -- 2.30.2