From 9ef1184d3516970e5be15897657699db64e03aad Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Mon, 9 May 2022 14:37:06 +0100 Subject: [PATCH] whitespace --- src/openpower/sv/trans/svp64.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py index 62baf5ec..620a9bdc 100644 --- a/src/openpower/sv/trans/svp64.py +++ b/src/openpower/sv/trans/svp64.py @@ -967,12 +967,12 @@ class SVP64Asm: if failfirst == 'RC1': mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing - assert rc_mode == False, "ffirst RC1 only possible when Rc=0" + assert rc_mode == False, "ffirst RC1 only ok when Rc=0" elif failfirst == '~RC1': mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing mode |= (0b1 << SVP64MODE.INV) # ... with inversion - assert rc_mode == False, "ffirst RC1 only possible when Rc=0" + assert rc_mode == False, "ffirst RC1 only ok when Rc=0" else: assert dst_zero == 0, "dst-zero not allowed in ffirst BO" assert rc_mode, "ffirst BO only possible when Rc=1" @@ -992,12 +992,12 @@ class SVP64Asm: if predresult == 'RC1': mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing - assert rc_mode == False, "pr-mode RC1 only possible when Rc=0" + assert rc_mode == False, "pr-mode RC1 only ok when Rc=0" elif predresult == '~RC1': mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing mode |= (0b1 << SVP64MODE.INV) # ... with inversion - assert rc_mode == False, "pr-mode RC1 only possible when Rc=0" + assert rc_mode == False, "pr-mode RC1 only ok when Rc=0" else: assert dst_zero == 0, "dst-zero not allowed in pr-mode BO" assert rc_mode, "pr-mode BO only possible when Rc=1" -- 2.30.2