From 9ef2e379843af6add4d3a34a7b2ef567d26b21fc Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 27 Jun 2020 20:12:02 +0100 Subject: [PATCH] increase (double) address width in TstL0CacheBuffer --- src/soc/experiment/l0_cache.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/experiment/l0_cache.py b/src/soc/experiment/l0_cache.py index c356e29b..f42545d5 100644 --- a/src/soc/experiment/l0_cache.py +++ b/src/soc/experiment/l0_cache.py @@ -266,7 +266,7 @@ class L0CacheBuffer(Elaboratable): class TstL0CacheBuffer(Elaboratable): def __init__(self, n_units=3, regwid=16, addrwid=4, ifacetype='testpi'): pspec = TestMemPspec(ldst_ifacetype=ifacetype, - addr_wid=addrwid, + addr_wid=addrwid<<1, mask_wid=8, reg_wid=regwid) self.cmpi = ConfigMemoryPortInterface(pspec) -- 2.30.2