From 9ef5e72917c8417c81ce863160cded94d7deb1de Mon Sep 17 00:00:00 2001
From: Derek Hower <drh5@cs.wisc.edu>
Date: Wed, 18 Nov 2009 11:55:30 -0600
Subject: [PATCH] ruby: added sequencer stats to track what requests are
 waiting on

---
 src/mem/ruby/system/Sequencer.cc | 40 +++++++++++++++++++++++++++-----
 src/mem/ruby/system/Sequencer.hh |  6 +++++
 src/mem/ruby/system/System.cc    |  4 ++++
 3 files changed, 44 insertions(+), 6 deletions(-)

diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 3e0997708..a8b4b075a 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -49,6 +49,10 @@ long int already = 0;
 Sequencer::Sequencer(const string & name)
   :RubyPort(name)
 {
+  m_store_waiting_on_load_cycles = 0;
+  m_store_waiting_on_store_cycles = 0;
+  m_load_waiting_on_store_cycles = 0;
+  m_load_waiting_on_load_cycles = 0;
 }
 
 void Sequencer::init(const vector<string> & argv)
@@ -143,6 +147,14 @@ void Sequencer::wakeup() {
   }
 }
 
+void Sequencer::printStats(ostream & out) const {
+  out << "Sequencer: " << m_name << endl;
+  out << "  store_waiting_on_load_cycles: " << m_store_waiting_on_load_cycles << endl;
+  out << "  store_waiting_on_store_cycles: " << m_store_waiting_on_store_cycles << endl;
+  out << "  load_waiting_on_load_cycles: " << m_load_waiting_on_load_cycles << endl;
+  out << "  load_waiting_on_store_cycles: " << m_load_waiting_on_store_cycles << endl;
+}
+
 void Sequencer::printProgress(ostream& out) const{
   /*
   int total_demand = 0;
@@ -354,8 +366,24 @@ void Sequencer::hitCallback(SequencerRequest* srequest, DataBlock& data) {
 
 // Returns true if the sequencer already has a load or store outstanding
 int Sequencer::isReady(const RubyRequest& request) {
-  if( m_writeRequestTable.exist(line_address(Address(request.paddr))) ||
-      m_readRequestTable.exist(line_address(Address(request.paddr))) ){
+  bool is_outstanding_store = m_writeRequestTable.exist(line_address(Address(request.paddr)));
+  bool is_outstanding_load = m_readRequestTable.exist(line_address(Address(request.paddr)));
+  if ( is_outstanding_store ) {
+    if ((request.type == RubyRequestType_LD) ||
+        (request.type == RubyRequestType_IFETCH) ||
+        (request.type == RubyRequestType_RMW_Read)) {
+      m_store_waiting_on_load_cycles++;
+    } else {
+      m_store_waiting_on_store_cycles++;
+    }
+    return LIBRUBY_ALIASED_REQUEST;
+  } else if ( is_outstanding_load ) {
+    if ((request.type == RubyRequestType_ST) ||
+        (request.type == RubyRequestType_RMW_Write) ) {
+      m_load_waiting_on_store_cycles++;
+    } else {
+      m_load_waiting_on_load_cycles++;
+    }
     return LIBRUBY_ALIASED_REQUEST;
   }
 
@@ -392,14 +420,14 @@ int64_t Sequencer::makeRequest(const RubyRequest & request)
       }
       issueRequest(request);
 
-    // TODO: issue hardware prefetches here
-    return id;
+      // TODO: issue hardware prefetches here
+      return id;
     }
     else {
       assert(0);
+      return 0;
     }
-  }
-  else {
+  } else {
     return ready;
   }
 }
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 52c7860d0..231df01bb 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -88,6 +88,7 @@ public:
   bool empty() const;
 
   void print(ostream& out) const;
+  void printStats(ostream & out) const;
   void checkCoherence(const Address& address);
 
   //  bool getRubyMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes);
@@ -127,6 +128,11 @@ private:
   bool m_deadlock_check_scheduled;
   int m_atomic_reads;
   int m_atomic_writes;
+
+  int m_store_waiting_on_load_cycles;
+  int m_store_waiting_on_store_cycles;
+  int m_load_waiting_on_store_cycles;
+  int m_load_waiting_on_load_cycles;
 };
 
 // Output operator declaration
diff --git a/src/mem/ruby/system/System.cc b/src/mem/ruby/system/System.cc
index ad67cdc80..4ce919618 100644
--- a/src/mem/ruby/system/System.cc
+++ b/src/mem/ruby/system/System.cc
@@ -335,6 +335,10 @@ void RubySystem::printStats(ostream& out)
 
   m_profiler_ptr->printStats(out);
   m_network_ptr->printStats(out);
+  for (map<string, Sequencer*>::const_iterator it = m_sequencers.begin();
+       it != m_sequencers.end(); it++) {
+    (*it).second->printStats(out);
+  }
   for (map<string, CacheMemory*>::const_iterator it = m_caches.begin();
        it != m_caches.end(); it++) {
     (*it).second->printStats(out);
-- 
2.30.2