From 9f09b4152ff1d5e83a126fc338ed58ca4887892c Mon Sep 17 00:00:00 2001 From: Richard Sandiford Date: Thu, 2 Sep 2004 18:36:16 +0000 Subject: [PATCH] mips.md (*lea_high64): Change split condition to flow2_completed. * config/mips/mips.md (*lea_high64): Change split condition to flow2_completed. Add a peephole2 to generate a more parallel version. From-SVN: r86975 --- gcc/ChangeLog | 5 +++++ gcc/config/mips/mips.md | 28 +++++++++++++++++++++++++++- 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 80d593f4bc6..f3bd2d417ea 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2004-09-02 Richard Sandiford + + * config/mips/mips.md (*lea_high64): Change split condition to + flow2_completed. Add a peephole2 to generate a more parallel version. + 2004-09-02 Jan Hubicka * gimplify.c (gimplify_compound_lval): Move "stack" varray out of diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 7fa4b08fa85..9c0b1ccfa6c 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -3103,12 +3103,15 @@ beq\t%2,%.,1b\;\ ;; dsll op0,op0,16 ;; daddiu op0,op0,%hi(op1) ;; dsll op0,op0,16 +;; +;; The split is deferred until after flow2 to allow the peephole2 below +;; to take effect. (define_insn_and_split "*lea_high64" [(set (match_operand:DI 0 "register_operand" "=d") (high:DI (match_operand:DI 1 "general_symbolic_operand" "")))] "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS" "#" - "&& reload_completed" + "&& flow2_completed" [(set (match_dup 0) (high:DI (match_dup 2))) (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2))) (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16))) @@ -3120,6 +3123,29 @@ beq\t%2,%.,1b\;\ } [(set_attr "length" "20")]) +;; Use a scratch register to reduce the latency of the above pattern +;; on superscalar machines. The optimized sequence is: +;; +;; lui op1,%highest(op2) +;; lui op0,%hi(op2) +;; daddiu op1,op1,%higher(op2) +;; dsll32 op1,op1,0 +;; daddu op1,op1,op0 +(define_peephole2 + [(match_scratch:DI 0 "d") + (set (match_operand:DI 1 "register_operand") + (high:DI (match_operand:DI 2 "general_symbolic_operand")))] + "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS" + [(set (match_dup 1) (high:DI (match_dup 3))) + (set (match_dup 0) (high:DI (match_dup 4))) + (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3))) + (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32))) + (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))] +{ + operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH); + operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW); +}) + ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit ;; SYMBOL_GENERAL X will take 6 cycles. This next pattern allows combine ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only -- 2.30.2